Real chip design and verification using Verilog and VHDL:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Los Angeles, Calif.
VhdlCohen Publ.
2002
|
| Subjects: | |
| Physical Description: | XXVIII, 394 S. graph. Darst. 1 CD-ROM (12 cm) |
| ISBN: | 0970539428 |
Staff View
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV019300037 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 040518s2002 d||| |||| 00||| eng d | ||
| 020 | |a 0970539428 |9 0-9705394-2-8 | ||
| 035 | |a (OCoLC)50263193 | ||
| 035 | |a (DE-599)BVBBV019300037 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-Aug4 | ||
| 050 | 0 | |a TK7885.7 | |
| 100 | 1 | |a Cohen, Ben |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Real chip design and verification using Verilog and VHDL |c Ben Cohen |
| 264 | 1 | |a Los Angeles, Calif. |b VhdlCohen Publ. |c 2002 | |
| 300 | |a XXVIII, 394 S. |b graph. Darst. |e 1 CD-ROM (12 cm) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Application specific integrated circuits |x Computer-aided design | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a Programmable logic devices |x Design | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-012768318 | ||
Record in the Search Index
| _version_ | 1804132707869917184 |
|---|---|
| any_adam_object | |
| author | Cohen, Ben |
| author_facet | Cohen, Ben |
| author_role | aut |
| author_sort | Cohen, Ben |
| author_variant | b c bc |
| building | Verbundindex |
| bvnumber | BV019300037 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)50263193 (DE-599)BVBBV019300037 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01114nam a2200337 c 4500</leader><controlfield tag="001">BV019300037</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">040518s2002 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0970539428</subfield><subfield code="9">0-9705394-2-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)50263193</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV019300037</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-Aug4</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7885.7</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Cohen, Ben</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Real chip design and verification using Verilog and VHDL</subfield><subfield code="c">Ben Cohen</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Los Angeles, Calif.</subfield><subfield code="b">VhdlCohen Publ.</subfield><subfield code="c">2002</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXVIII, 394 S.</subfield><subfield code="b">graph. Darst.</subfield><subfield code="e">1 CD-ROM (12 cm)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Datenverarbeitung</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Application specific integrated circuits</subfield><subfield code="x">Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic design</subfield><subfield code="x">Data processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Programmable logic devices</subfield><subfield code="x">Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">VHDL (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-012768318</subfield></datafield></record></collection> |
| id | DE-604.BV019300037 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:57:06Z |
| institution | BVB |
| isbn | 0970539428 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012768318 |
| oclc_num | 50263193 |
| open_access_boolean | |
| owner | DE-Aug4 |
| owner_facet | DE-Aug4 |
| physical | XXVIII, 394 S. graph. Darst. 1 CD-ROM (12 cm) |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | VhdlCohen Publ. |
| record_format | marc |
| spelling | Cohen, Ben Verfasser aut Real chip design and verification using Verilog and VHDL Ben Cohen Los Angeles, Calif. VhdlCohen Publ. 2002 XXVIII, 394 S. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| spellingShingle | Cohen, Ben Real chip design and verification using Verilog and VHDL Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| title | Real chip design and verification using Verilog and VHDL |
| title_auth | Real chip design and verification using Verilog and VHDL |
| title_exact_search | Real chip design and verification using Verilog and VHDL |
| title_full | Real chip design and verification using Verilog and VHDL Ben Cohen |
| title_fullStr | Real chip design and verification using Verilog and VHDL Ben Cohen |
| title_full_unstemmed | Real chip design and verification using Verilog and VHDL Ben Cohen |
| title_short | Real chip design and verification using Verilog and VHDL |
| title_sort | real chip design and verification using verilog and vhdl |
| topic | Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| topic_facet | Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| work_keys_str_mv | AT cohenben realchipdesignandverificationusingverilogandvhdl |