Real chip design and verification using Verilog and VHDL:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Angeles, Calif.
VhdlCohen Publ.
2002
|
| Schlagworte: | |
| Beschreibung: | XXVIII, 394 S. graph. Darst. 1 CD-ROM (12 cm) |
| ISBN: | 0970539428 |
Internformat
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| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Application specific integrated circuits |x Computer-aided design | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a Programmable logic devices |x Design | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-012768318 | ||
Datensatz im Suchindex
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| id | DE-604.BV019300037 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:57:06Z |
| institution | BVB |
| isbn | 0970539428 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012768318 |
| oclc_num | 50263193 |
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| physical | XXVIII, 394 S. graph. Darst. 1 CD-ROM (12 cm) |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | VhdlCohen Publ. |
| record_format | marc |
| spelling | Cohen, Ben Verfasser aut Real chip design and verification using Verilog and VHDL Ben Cohen Los Angeles, Calif. VhdlCohen Publ. 2002 XXVIII, 394 S. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| spellingShingle | Cohen, Ben Real chip design and verification using Verilog and VHDL Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| title | Real chip design and verification using Verilog and VHDL |
| title_auth | Real chip design and verification using Verilog and VHDL |
| title_exact_search | Real chip design and verification using Verilog and VHDL |
| title_full | Real chip design and verification using Verilog and VHDL Ben Cohen |
| title_fullStr | Real chip design and verification using Verilog and VHDL Ben Cohen |
| title_full_unstemmed | Real chip design and verification using Verilog and VHDL Ben Cohen |
| title_short | Real chip design and verification using Verilog and VHDL |
| title_sort | real chip design and verification using verilog and vhdl |
| topic | Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| topic_facet | Datenverarbeitung Application specific integrated circuits Computer-aided design Logic design Data processing Programmable logic devices Design VHDL (Computer hardware description language) Verilog (Computer hardware description language) |
| work_keys_str_mv | AT cohenben realchipdesignandverificationusingverilogandvhdl |