APA (7th ed.) Citation

Cohen, B. (2002). Real chip design and verification using Verilog and VHDL. VhdlCohen Publ.

Chicago Style (17th ed.) Citation

Cohen, Ben. Real Chip Design and Verification Using Verilog and VHDL. Los Angeles, Calif: VhdlCohen Publ, 2002.

MLA (9th ed.) Citation

Cohen, Ben. Real Chip Design and Verification Using Verilog and VHDL. VhdlCohen Publ, 2002.

Warning: These citations may not always be 100% accurate.