Starter's guide to Verilog 2001:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Upper Saddle River, N.J.
Pearson Prentice Hall
2004
|
| Edition: | 1. print. |
| Subjects: | |
| Physical Description: | XIV, 234 S. graph. Darst. |
| ISBN: | 0131415565 |
Staff View
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| 264 | 1 | |a Upper Saddle River, N.J. |b Pearson Prentice Hall |c 2004 | |
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Record in the Search Index
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| any_adam_object | |
| author | Ciletti, Michael D. |
| author_facet | Ciletti, Michael D. |
| author_role | aut |
| author_sort | Ciletti, Michael D. |
| author_variant | m d c md mdc |
| building | Verbundindex |
| bvnumber | BV017367164 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)52631076 (DE-599)BVBBV017367164 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1. print. |
| format | Book |
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| id | DE-604.BV017367164 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:17:11Z |
| institution | BVB |
| isbn | 0131415565 |
| language | English |
| lccn | 2003059652 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010467320 |
| oclc_num | 52631076 |
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| owner | DE-573 |
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| physical | XIV, 234 S. graph. Darst. |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Pearson Prentice Hall |
| record_format | marc |
| spelling | Ciletti, Michael D. Verfasser aut Starter's guide to Verilog 2001 Michael D. Ciletti 1. print. Upper Saddle River, N.J. Pearson Prentice Hall 2004 XIV, 234 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 |
| spellingShingle | Ciletti, Michael D. Starter's guide to Verilog 2001 Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Starter's guide to Verilog 2001 |
| title_auth | Starter's guide to Verilog 2001 |
| title_exact_search | Starter's guide to Verilog 2001 |
| title_full | Starter's guide to Verilog 2001 Michael D. Ciletti |
| title_fullStr | Starter's guide to Verilog 2001 Michael D. Ciletti |
| title_full_unstemmed | Starter's guide to Verilog 2001 Michael D. Ciletti |
| title_short | Starter's guide to Verilog 2001 |
| title_sort | starter s guide to verilog 2001 |
| topic | Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG |
| work_keys_str_mv | AT cilettimichaeld startersguidetoverilog2001 |