Starter's guide to Verilog 2001:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, N.J.
Pearson Prentice Hall
2004
|
| Ausgabe: | 1. print. |
| Schlagworte: | |
| Beschreibung: | XIV, 234 S. graph. Darst. |
| ISBN: | 0131415565 |
Internformat
MARC
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| 035 | |a (OCoLC)52631076 | ||
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| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c US | ||
| 049 | |a DE-573 | ||
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| 082 | 0 | |a 621.39/2 |2 22 | |
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| 100 | 1 | |a Ciletti, Michael D. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Starter's guide to Verilog 2001 |c Michael D. Ciletti |
| 250 | |a 1. print. | ||
| 264 | 1 | |a Upper Saddle River, N.J. |b Pearson Prentice Hall |c 2004 | |
| 300 | |a XIV, 234 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Electronic digital computers |x Design and construction | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-010467320 | ||
Datensatz im Suchindex
| _version_ | 1804130195769131008 |
|---|---|
| any_adam_object | |
| author | Ciletti, Michael D. |
| author_facet | Ciletti, Michael D. |
| author_role | aut |
| author_sort | Ciletti, Michael D. |
| author_variant | m d c md mdc |
| building | Verbundindex |
| bvnumber | BV017367164 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)52631076 (DE-599)BVBBV017367164 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1. print. |
| format | Book |
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| id | DE-604.BV017367164 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:17:11Z |
| institution | BVB |
| isbn | 0131415565 |
| language | English |
| lccn | 2003059652 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010467320 |
| oclc_num | 52631076 |
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| owner | DE-573 |
| owner_facet | DE-573 |
| physical | XIV, 234 S. graph. Darst. |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Pearson Prentice Hall |
| record_format | marc |
| spelling | Ciletti, Michael D. Verfasser aut Starter's guide to Verilog 2001 Michael D. Ciletti 1. print. Upper Saddle River, N.J. Pearson Prentice Hall 2004 XIV, 234 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 |
| spellingShingle | Ciletti, Michael D. Starter's guide to Verilog 2001 Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Starter's guide to Verilog 2001 |
| title_auth | Starter's guide to Verilog 2001 |
| title_exact_search | Starter's guide to Verilog 2001 |
| title_full | Starter's guide to Verilog 2001 Michael D. Ciletti |
| title_fullStr | Starter's guide to Verilog 2001 Michael D. Ciletti |
| title_full_unstemmed | Starter's guide to Verilog 2001 Michael D. Ciletti |
| title_short | Starter's guide to Verilog 2001 |
| title_sort | starter s guide to verilog 2001 |
| topic | Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Electronic digital computers Design and construction Verilog (Computer hardware description language) VERILOG |
| work_keys_str_mv | AT cilettimichaeld startersguidetoverilog2001 |