A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Düsseldorf
VDI-Verl.
2003
|
| Ausgabe: | Als Ms. gedr. |
| Schriftenreihe: | Fortschritt-Berichte VDI
Reihe 20, Rechnerunterstützte Verfahren ; 367 |
| Schlagworte: | |
| Beschreibung: | X, 99 S. graph. Darst. |
| ISBN: | 3183367203 |
Internformat
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Datensatz im Suchindex
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| author | Harbich, Klaus 1968- |
| author_GND | (DE-588)128626208 |
| author_facet | Harbich, Klaus 1968- |
| author_role | aut |
| author_sort | Harbich, Klaus 1968- |
| author_variant | k h kh |
| building | Verbundindex |
| bvnumber | BV017238962 |
| classification_rvk | ZN 4904 |
| ctrlnum | (OCoLC)54928665 (DE-599)BVBBV017238962 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Als Ms. gedr. |
| format | Thesis Book |
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| genre_facet | Hochschulschrift |
| id | DE-604.BV017238962 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:15:25Z |
| institution | BVB |
| isbn | 3183367203 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010388851 |
| oclc_num | 54928665 |
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| physical | X, 99 S. graph. Darst. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | VDI-Verl. |
| record_format | marc |
| series | Fortschritt-Berichte VDI |
| series2 | Fortschritt-Berichte VDI : Reihe 20, Rechnerunterstützte Verfahren |
| spelling | Harbich, Klaus 1968- Verfasser (DE-588)128626208 aut A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems Klaus Harbich Als Ms. gedr. Düsseldorf VDI-Verl. 2003 X, 99 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Fortschritt-Berichte VDI : Reihe 20, Rechnerunterstützte Verfahren 367 Zugl.: Hannover, Univ., Diss., 2003 Register-Transfer-Ebene (DE-588)4215789-4 gnd rswk-swf Block-Layout (DE-588)4264877-4 gnd rswk-swf Platzierung Mikroelektronik (DE-588)4197293-4 gnd rswk-swf Rapid Prototyping (DE-588)4592693-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Timingsimulation (DE-588)4388820-3 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Rapid Prototyping (DE-588)4592693-1 s Field programmable gate array (DE-588)4347749-5 s Register-Transfer-Ebene (DE-588)4215789-4 s Block-Layout (DE-588)4264877-4 s Timingsimulation (DE-588)4388820-3 s Platzierung Mikroelektronik (DE-588)4197293-4 s DE-604 Fortschritt-Berichte VDI Reihe 20, Rechnerunterstützte Verfahren ; 367 (DE-604)BV021786833 367 |
| spellingShingle | Harbich, Klaus 1968- A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems Fortschritt-Berichte VDI Register-Transfer-Ebene (DE-588)4215789-4 gnd Block-Layout (DE-588)4264877-4 gnd Platzierung Mikroelektronik (DE-588)4197293-4 gnd Rapid Prototyping (DE-588)4592693-1 gnd Field programmable gate array (DE-588)4347749-5 gnd Timingsimulation (DE-588)4388820-3 gnd |
| subject_GND | (DE-588)4215789-4 (DE-588)4264877-4 (DE-588)4197293-4 (DE-588)4592693-1 (DE-588)4347749-5 (DE-588)4388820-3 (DE-588)4113937-9 |
| title | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems |
| title_auth | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems |
| title_exact_search | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems |
| title_full | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems Klaus Harbich |
| title_fullStr | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems Klaus Harbich |
| title_full_unstemmed | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems Klaus Harbich |
| title_short | A timing-driven RTL-based design flow for multi-FPGA rapid prototyping systems |
| title_sort | a timing driven rtl based design flow for multi fpga rapid prototyping systems |
| topic | Register-Transfer-Ebene (DE-588)4215789-4 gnd Block-Layout (DE-588)4264877-4 gnd Platzierung Mikroelektronik (DE-588)4197293-4 gnd Rapid Prototyping (DE-588)4592693-1 gnd Field programmable gate array (DE-588)4347749-5 gnd Timingsimulation (DE-588)4388820-3 gnd |
| topic_facet | Register-Transfer-Ebene Block-Layout Platzierung Mikroelektronik Rapid Prototyping Field programmable gate array Timingsimulation Hochschulschrift |
| volume_link | (DE-604)BV021786833 |
| work_keys_str_mv | AT harbichklaus atimingdrivenrtlbaseddesignflowformultifpgarapidprototypingsystems |