CMOS logic circuit design:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Boston [u.a.]
Kluwer
2003
|
| Edition: | 4. printing |
| Subjects: | |
| Physical Description: | XVIII, 528 S. graph. Darst. |
| ISBN: | 0792384520 |
Staff View
MARC
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| 245 | 1 | 0 | |a CMOS logic circuit design |c John P. Uyemura |
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Record in the Search Index
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| any_adam_object | |
| author | Uyemura, John P. |
| author_facet | Uyemura, John P. |
| author_role | aut |
| author_sort | Uyemura, John P. |
| author_variant | j p u jp jpu |
| building | Verbundindex |
| bvnumber | BV017164571 |
| callnumber-first | T - Technology |
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| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 358f ELT 272f ELT 456f |
| ctrlnum | (OCoLC)249382312 (DE-599)BVBBV017164571 |
| dewey-full | 621.39/732 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/732 |
| dewey-search | 621.39/732 |
| dewey-sort | 3621.39 3732 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 4. printing |
| format | Book |
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| id | DE-604.BV017164571 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:14:31Z |
| institution | BVB |
| isbn | 0792384520 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010347879 |
| oclc_num | 249382312 |
| open_access_boolean | |
| owner | DE-29T DE-91 DE-BY-TUM |
| owner_facet | DE-29T DE-91 DE-BY-TUM |
| physical | XVIII, 528 S. graph. Darst. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer |
| record_format | marc |
| spelling | Uyemura, John P. Verfasser aut CMOS logic circuit design John P. Uyemura 4. printing Boston [u.a.] Kluwer 2003 XVIII, 528 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier CMOS (DE-588)4010319-5 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 s VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s CMOS (DE-588)4010319-5 s 1\p DE-604 Digitale integrierte Schaltung (DE-588)4113313-4 s 2\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Uyemura, John P. CMOS logic circuit design CMOS (DE-588)4010319-5 gnd Logische Schaltung (DE-588)4131023-8 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Entwurf (DE-588)4121208-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd VLSI (DE-588)4117388-0 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd |
| subject_GND | (DE-588)4010319-5 (DE-588)4131023-8 (DE-588)4148111-2 (DE-588)4121208-3 (DE-588)4179389-4 (DE-588)4117388-0 (DE-588)4113313-4 |
| title | CMOS logic circuit design |
| title_auth | CMOS logic circuit design |
| title_exact_search | CMOS logic circuit design |
| title_full | CMOS logic circuit design John P. Uyemura |
| title_fullStr | CMOS logic circuit design John P. Uyemura |
| title_full_unstemmed | CMOS logic circuit design John P. Uyemura |
| title_short | CMOS logic circuit design |
| title_sort | cmos logic circuit design |
| topic | CMOS (DE-588)4010319-5 gnd Logische Schaltung (DE-588)4131023-8 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Entwurf (DE-588)4121208-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd VLSI (DE-588)4117388-0 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd |
| topic_facet | CMOS Logische Schaltung CMOS-Schaltung Entwurf Schaltungsentwurf VLSI Digitale integrierte Schaltung |
| work_keys_str_mv | AT uyemurajohnp cmoslogiccircuitdesign |