Verfügbarkeit: ICCAD 2002 :: THWS Bibkatalog

ICCAD 2002: November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]

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Bibliographische Detailangaben
Körperschaft:	International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif (VerfasserIn)
Format:	Tagungsbericht Buch
Sprache:	English
Veröffentlicht:	Piscataway, NJ IEEE [u.a.] 2002
Schlagworte:	CAD Konferenzschrift > 2002 > San Jose, Calif.
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XXX, 798 S. Ill., graph. Darst.
ISBN:	0780376072

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adam_text	Table of Contents Foreword . iii Conference Committee .iv Technical Program Committee .xix Reviewers .xxi Awards .xxiii Keynote .xxiv Tutorial 1: High Performance Integrated Circuit Analysis · · · xxv and Design Including On-Chip Inductance Tutorial 2: FPGAs: Computer-Aided Design, .xxvi Applications and Future Architectures Tutorial 3: Specification and Design of Multimillion .xxvii Gate SOCs Tutorial 4: Placement - The Key Problem in Physical · · · · xxviii Design Panel: Open Source: EDA's Next Wave or .xxix Yesterday's Hype? Panel: CAD for CAD's Sake? Are CAD and .xxx Design Diverging? Session 1A: Substrate Modeling Moderators: Eli Chiprout, Intel Corp., Chandler, AZ Sharad Kapur, Agere Systems, Inc., Murray Hill, NJ 1A.1 Comprehensive Frequency-Dependent Substrate Noise Analysis Using .2 Boundary Element Methods Hongmei Li, Jorge Carballido, Harry H. Yu, Vladimir 1. Okhmatovski, Ely se Rosenbaum and Andreas C. Cangellaris 1A.2 Theoretical and Practical Validation of Combined BEM/FEM .10 Substrate Resistance Modeling E. Schrik, P.M. Dewilde and N.P. van der Meijs 1A.3 Implicit Treatment of Substrate and Power-Ground Losses .16 in Return-limited Inductance Extraction Dipak Sitaram, Yu Zheng and Kenneth L Shepard Session IB: Invited Session: Design for Low-Power Moderators: Bořivoje Nikolic, University of California, Berkeley, С А Lawrence T. Fileggi, Carnegie Mellon University, Pittsburgh, PA 1B.1 Minimizing Power Across Multiple Technology and Design Levels .24 Takayasu Sakurai 1B.2 Optimization and Control of VDD and VTH for Low-Power, .28 High-Speed CMOS Design Tadahiro Kuroda 1B.3 Methods for True Power Minimization .35 Robert W. Brodersen, Mark A. Horowitz, Dejan Markovic, Bořivoje Nikolic and Vladimir Stojanovic Session 1С: Routing Moderators: Tong Gao, Monterey Design Systems, Sunnyvale, CA Charles J. Alpert, IBM Corp., Austin, TX ICI A Novel Framework for Multilevel Routing Considering Routability .44 and Performance Shih-Ping Lin and Yao-Wen Chang 1C.2 An Enhanced Multilevel Routing System .51 Jason Cong, Min Xie and Y an Zhang 1С J Track Assignment: A Desirable Intermediate Step Between Global .59 Routing and Detailed Routing Shabbir Batterywala, Narendra Shenoy, William Nicholls and Hai Zhou 1C.4 ECO Algorithms for Removing Overlaps Between Power Rails .67 and Signal Wires Hua Xiang, Kai-Yuan Chao and D.F. Wong Session ID: Advances in Testing Moderators: Tomoo Inoue, Hiroshima City University, Hiroshima, Japan M. Jeske-Chrzanowska, Portland University, Portland, OR 1D.1 Fast Seed Computation for Reseeding Shift Register in Test Pattern .76 Compression Nahmsuk Oh, Rohit KapurandT.W. Williams 1D.2 On Undetectable Faults in Partial Scan Circuits .82 Irith Pomeranz and Sudhakar M. Reddy VI 1D.3 Conflict Driven Techniques for Improving Deterministic Test Pattern .87 Generation Chen Wang, Sudhakar M. Reddy, Irith Pomeraní, Xijiang Un and Janusz Rajski 1D.4 On Theoretical and Practical Considerations of Path Selection for .94 Delay Fault Testing Jing-Jia Liou, Li-C. Wang and Kwang-Ting Cheng Session 2A: Novel Ideas in High Level Synthesis Moderators: Julio L· da Silva, GetŽChip.com, Inc., San Jose, CA Patrick R. Schaumont, University of California, Los Angeles, С А 2A.1 Interface Specification for Reconfigurable Components .102 Satnam Singh 2A.2 Interconnect-aware High-level Synthesis for Low Power .110 Lin Zhong and Niraj K. Jha 2A.3 Predictability: Definition, Analysis and Optimization .118 Ankur Srivastava and Majid Sarrafzadeh Session 2B: Formal Techniques for Validation and Synthesis Moderators: Aarti Gupta, NEC USA, Inc., Princeton, NJ Rajeev Ranjan, Real Intent, Santa Clara, CA 2B.1 Symplifying Boolean Constraint Solving for Random .123 Simulation-Vector Generation Jun Yuan, Ken Albin, Adrian Aziz and Carl Pixley 2B.2 Specifying and Verifying Imprecise Sequential Datapaths by .128 Arithmetic Transforms Katarzyna Radecka and Zeljko Zilic 2ЂЈЗ Convertibility Verification and Converter Synthesis: Two Faces of .132 the Same Coin Roberto Passerone, Luca de Alfaro, Thomas A. Henzinger and Alberto L· Sangiovanni-Vincentelli Session 2C: Embedded Tutorial: Subthreshold Leakage Modeling and Reduction Techniques Moderators: Georges Gielen, Katholieke University, Leuven, Belgium FaridN. Najm, University of Toronto, Toronto, Ontario, Canada 2C.1 Subthreshold Leakage Modeling and Reduction Techniques .141 Jams Kao, Siva Narendra and Anantha Chandrakasan vu Session ЗА: Compilation Techniques for Hardware/Software Codesign Moderators: Joerg Henkel, NEC USA, Inc., Princeton, NJ Luc Semeria, Synopsys, Inc., Mountain View, CA 3A.1 Symbolic Pointer Analysis .150 Jianwen Zhu 3A.2 Dynamic Compilation for Energy Adaptation .158 P. Unnikrishnan, G. Chen, M. Kandemir and D.R. Mudgett 3A.3 Hardware/Soft ware Partitioning of Software Binaries .164 Greg Stitt and Frank Vahid Session 3B: Timing-Driven Placement Moderators: Rajeev Jayaraman, Xilinx, Inc., San Jose, CA Jens Vygen, Bonn University, Bonn, Germany 3B.1 A Novel Net Weighting Algorithm for Timing-Driven Placement. 172 Tim (Tianming) Kong 3B.2 Timing-Driven Placement using Design Hierarchy Guided Constraint . 177 Generation Xiaojian Yang, Bo-Kyung Choi and Majid Sarrafzadeh 3B.3 Multi-objective Circuit Partitioning for Cutsize and Path-Based .181 Delay Minimization Cristinel Ababei, Selvakkumaran Navaratnasothie, Kia Bazargan and George Karypis Session 3C: Invited Session: Emerging Technology Opportunities and Challenges Moderators: Makoto Ikeda, University of Tokyo, Tokyo, Japan Andreas Kuehlmann, Cadence Berkeley Labs., Berkeley, С А 3d A Hybrid ASIC and FPGA Architecture .187 PaulS. Zuchowski, Christopher B. Reynolds, Richard J . Grupp, Shelly G. Davis, Brendan Cremen and Bill Troxel 3C.2 Managing Power and Performance for System-on-Chip Designs .195 using Voltage Islands DavidE. Lackey, PaulS. Zuchowski, Thomas R. Bednár, Douglas W. Stout, Scott W. Gould and John M. Cohn 3O3 Sub-Wnra Technologies- Challenges and Opportunities for CAD .203 Tanay Karvik, Shekhar Borkar and Vivek De VIII Session 3D: Inductance Modeling I Moderators: Eli Chiprout, Intel Corp., Chandler, AZ Mustafa Ceük, Magma Design Automation, Inc., Cupertino, С А 3D.1 A Local Circuit Topology for Inductive Parasitics .208 Andrea Pacelli 3D.2 INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor . 215 Tsung-Hao Chen, Clement Luk, Hyungsuk Kim and Charlie Chung-Ping Chen 3D.3 A Precorrected-FFT Method for Simulating On-chip Inductance .221 Haitian Ни, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda and Sachin S. Sapatnekar Session 4A: Efficient Simulation for Analog and RF Moderators: Helmut E. Graeb, Technical University of Munich, Munich, Germany Ken Kundért, Cadence Design Systems, Inc., San Jose, С А 4A.1 On the Difference between Two Widely Publicized Methods for .229 Analyzing Oscillator Phase Behavior Piet Vanassche, Georges Gielen and Willy Sansen 4A.2 A Behavioral Simulation Tool for Continuous-Time Delta-Sigma .234 Modulators K. Francken, M. Vogels, E. Martens and Georges Gielen 4A.3 Making Fourier-Envelope Simulation Robust .240 Jiajeet Roychowdhury Session 4B: Interconnect Optimization Moderators: Cheng -Кок Koh, Purdue University, West Lafayette, IN Charles Chiang, Synopsys, Inc., Mountain View, CA 4B.1 Optimal Buffered Routing Path Constructions for Single and Multiple . 247 Clock Domain Systems Soha Hassoun, Charles J. Alpert and Meera Thiagarajan 4B.2 Shaping Interconnect for Uniform Current Density .254 Muzhou Shao, D.F. Wong, Youxin Gao, Li -Реп Yuan andHuijing Cao 4B.3 Non-tree Routing for Reliability and Yield Improvement .260 Andrew B. Kahng, Bao Liu and Ion I. Mandoiu IX Session 4C: Chip-Level Communication Structures Moderators: Leon Stok, IBM Corp., Yorktown Heights, NY Dwight Hill, Synopsys, Inc., Mountain View, CA 4C.1 Concurrent Flip-Flop and Repeater Insertion for High Performance.268 Integrated Circuits Pasquale Cocchini 4C.2 Throughput-Driven 1С Communication Fabric Synthesis. 274 Tao Lin and Lawrence T. Fileggi 4C.3 Repeater Insertion and Wire Sizing Optimization for .280 Throughput-Centric VLSI Global Interconnects Harshit Shah, Pun Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory and Jeff Davis Session 4D: New DFT Techniques and Methodologies Moderators: Božena Kaminska, ЗМТ Solutions, Lake Oswego, OR Tomoo Inoue, Hiroshima City University, Hiroshima, Japan 4D.1 Test-Model based Hierarchical DFT Synthesis .286 Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech and Felix Ng 4D.2 Characteristic Faults and Spectral Information for Logic BIST .294 Xiaoding Chen and Michael S. Hsiao 4D.3 A Novel Scan Architecture for Power-Efficient, Rapid Test .299 Ozgur Sinanoglu and Alex Orailoglu Session 5A: System-Level Analog Design Moderators: Jaijeet Roychowdhury, University of Minnesota, Minneapolis, MN Henry Chang, Cadence Design Systems, Inc., San Jose, С А 5A.1 Optimization of a Fully Integrated Low Power CMOS GPS Receiver .305 Peter Vancoreland, Philippe Coppejans, Wouter De Cock, Paul Leroux and Michiel Steyaert 5AJ2 Analysis and Optimization of Substrate Noise Coupling in Single-Chip . 309 RF Transceiver Design Adii Koukab, Kaustav Banerjee and Michel Declercq 5A.3 Design of Pipeline Analog-to-Digital Converters via Geometric .317 Programming Maria del Mar Hershenson Session 5В: Inductance Modelling II Moderators: Kenneth L· Shepard, Columbia University, New York, NY Mattan Kamon, Coventor, Inc., Cambridge, MA 5B.1 Proximity Templates for Modeling of Skin and Proximity Effects on .326 Packages and High Frequency Interconnect Luca Daniel, Alberto L. Sangiovanni-Vincentelli and Jacob K. White 5B.2 Transmission Line Design of Clock Trees .334 Rafael Escovar and Robert Suaya 5B.3 On-chip Interconnect Modeling by Wire Duplication .341 Guoan Zhong, Cheng -Кок Koh and Kaushik Roy Session 5C: Emerging Technologies: Circuits and Systems Moderators: Mary Ann Maher, MEMSCAP, Inc., Oakland, CA Michael Butts, Cadence Design Systems, Inc., Portland, OR 5C.1 A Case for CMOS/nano Co-design .348 Matthew M. Ziegler and Mircea R. Stan 5C.2 Reversible Logic Circuit Synthesis .353 Vivek V. Shende, Aditya K. Prasad, Igor L. Markov and John P. Hayes 5C.3 Extraction and LVS for Mixed-domain Integrated MEMS Layouts .361 Bikram Baidya and Tamal Mukherjee 5C.4 Schematic-Based Lumped Parameterized Behavioral Modeling .367 for Suspended MEMS Qi Jing, Tamal Mukherjee and Gary K. Fedder Session 5D: Low Power and Transistor Level Optimization Moderators: Rajeev Murgai, Fujitsu Labs, of America, Sunnyvale, CA Michel Berklaar, Magma Design Automation, Inc., Eindhoven, The Netherlands 5D.1 Standby Power Optimization via Transistor Sizing and Dual Threshold. . . . 375 Voltage Assignment Mahesh Ketkar and Sachin S. Sapatnekar 5D.2 Power Efficiency of Voltage Scaling in Multiple Clock, Multiple .379 Voltage Cores Anoop Iyer and Diana Marculescu 5D3 Optimized Power-Delay Curve Generation for Standard Cell ICs .387 Miodrag Vujkovic and Carl Sechen χι 5D.4 Gate Sizing Using Lagrangian Relaxation Combined with a Fast .395 Gradient-Based Pre-Processing Step Hiran Tennakoon and Carl Sechen Session 6A: Statistical Techniques for Power and Timing Estimation Moderators: F arid N. Najm, University of Toronto, Toronto, Ontario, Canada Dennis M. Sylvester, University of Michigan, Ann Arbor, MI 6A.1 A Markov Chain Sequence Generator for Power Macromodeling .404 Xun Liu and Marios C. Papaefthymiou 6A.2 Circuit Power Estimation using Pattern Recognition Techniques .412 Lipeng Cao 6A.3 Estimation of Signal Arrival Times in the Presence of Delay Noise .418 Sarvesh Bhardwaj, Sarma В. К. Vrudhula and David Blaauw Session 6B: Embedded Tutorial: CAD Computation for Manufacturability: Can We Save VLSI Technology From Itself? Moderators: Andrzej Strojwas, Carnegie Mellon University, Pittsburgh, PA Andrew B. Kahng, University of California at San Diego, La J olla, CA 6B.1 CAD Computation for Manufacturability: Can We Save VLSI .424 Technology from Itself? Mark Lavin and Lars Liebmann Session 6C: Embedded Tutorial: Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips Moderators: Paul D. Franzon, North Carolina State University, Raleigh, NC Tamal Mukherjee, Carnegie Mellon University, Pittsburgh, PA 6C.1 Molecular Electronics: Devices, Systems and Tools for Gigagate, .433 Gigabit Chips Michael Butts, Andre DeHon and Seth Copen Goldstein Session 7A: Satisfiability Checking Moderators: Armin Biere, ΕΤΗ Zurich, Zurich, Switzerland James H. Kukula, Synopsys, Inc., Hühboro, OR 7A.1 Conflict Driven Learning in a Quantified Boolean Satisfiability Solver . 442 Lintao Zhang and Sharad Malik 7АЛ Generic ILP versus Specialized 0-1 ILP: An Update .450 F adi A. Aloul, Arathi Romani, Igor L Markov and Karem A. Sakallah xu 7A.3 Binary Time-Frame Expansion .458 Farzan Fallah Session 7B: Emerging Technologies: Device Modeling and Simulation Moderators: Joel R. Phillips, Cadence Berkeley Labs., San Jose, CA Narayan R. Aluru, University of Illinois, Urbana, IL 7B.1 Fast Methods for Simulation of Biomolecule Electrostatics .466 Shihhsien S. Kuo, Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor and Jacob K. White 7B.2 Efficient Mixed-Domain Analysis of Electrostatic MEMS .474 Gang Li and Narayan R. Aluru 7B.3 FastMag: A 3-D Magnetostatic Inductance Extraction Program for .478 Structures with Permeable Materials Yehia Massoud and Jacob K. White Session 7C: Circuit-Level Analog CAD Moderators: Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA Henry Chang, Cadence Design Systems, Inc., San Jose, CA 7C.1 Analog Circuit Sizing Based on Formal Methods Using Affine Arithmetic . . 486 Andreas Lemke, Lars Hedrich and Erich Barke 7C.2 SiSMA: A Statistical Simulator for Mismatch Analysis of MOS ICs .490 G. Biagetti, S. Ordoni, L. Signoracci, С. Turchetti, P. Crippa andM. Alessandrini 7C.3 Efficient Solution Space Exploration Based on Segment Trees in .497 Analog Placement with Symmetry Constraints Florin Balosa, Sarat С. Maruvada and Karthik Krishnamoorthy Session 7D: Physical Effects in Deep Sub Micron Technology Moderators: Ron Duncan, Synopsys, Inc., Fremont, CA Michel Laudes, Sun Microsystems, Inc., Sunnyvale, CA 7D.1 Post Global Routing RLC Crosstalk Budgeting .504 Jinjun Xiong, Jun Chen, James Ma and Lei He 7D.2 A Technology-independent CAD Tool For ESD Protection Device .510 Extraction — ESDExtractor R.Y. Zhan, H.G. Feng, Q. Wu, G. Chen, XX. Guan and Albert Z. Wang 7DJ On Mask Layout Partitioning for Electron Projection Lithography .514 Ruiqi Tian, Ronggang Yu, Xiaoping Tang andD.F. Wong xm Session 8A: Verification at the Switch, Gate, and RT Levels Moderators: Ken MacMillan, Cadence Berkeley Labs., Berkeley, CA Alan Ни, University of British Columbua, Vancouver, ВС, Canada 8A.1 High Capacity and Automatic Functional Extraction Tool for .520 Industrial VLSI Circuit Designs Sasha Novakovsky, Shy Shyman and Ziyad Hanna 8A.2 Combinational Equivalence Checking through Function Transformation. . . 526 Нее Hwan Kwak, In-Ho Moon, James H. Kukula and Thomas R. Shiple 8A.3 GSTE Through a Case Study .534 Jin Yang and Amit Goei Session 8B: New Trends in Logic Synthesis Moderators: Hamid Savoj, Magma Design Automation, Cupertino, CA Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA 8B.1 Whirlpool PLAs: A Regular Logic Structure and Their Synthesis .543 Fan Mo and Robert K. Brayton 8B.2 Metrics for Structural Logic Synthesis .551 Prabhakar Kudva, Andrew Sullivan and William Dougherty 8BJ Simplification of Non-Deterministic Multi-Valued Networks .557 Alan Mishchenko and Robert K. Brayton Session 8C: Memory Issues in High-Level Synthesis Moderators: Allen C.-H. Wu, National Tsing Hua University, Hsinchu, Taiwan, ROC Loganath Ramachandran, Synopsys, Inc., Mountain View, CA 8C.1 High-Level Synthesis of Distributed Logic-Memory Architectures .564 Chao Huang, Srivaths Ravi, Anand Raghunathan and Niraj K. Jha 8C.2 An Energy-conscious Algorithm for Memory Port Allocation .572 Preeti Ranjan Panda and Lakshmikantam Chitturi 8C3 Energy Efficient Address Assignment Through Minimized Memory .577 Row Switching Sambuddhi Hettiaratchi, Peter Y.K. Cheung and Thomas J.W. Clarke XIV Session 8D: Noise Effects on Circuit Operation Moderators: Florentin Dartu, Intel Corp., Hillsboro, OR Anirudh Devgan, IBM Corp., Austin, TX 8D.1 Refining Switching Window by Time Slots for Crosstalk Noise Calculation. . 583 Pinhong Chen, Yuji Kukimoto and Kurt Keutzer 8D.2 Noise Propagation and Failure Criteria for VLSI Designs .587 V. Zolotov, David Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon and R. Levy 8D.3 Efficient Crosstalk Noise Modeling Using Aggressor and Tree Reductions . . 595 Li Ding, David Blaauw and Pinaki Mazumder Session 9A: Low Level Aware Behavioral Synthesis Moderators: Forrest D. Brewer, University of California, Santa Barbara, С А Barry Pangrle, Synopsys, Inc., Mountain View, CA 9A.1 Bit-level Scheduling of Heterogeneous Behavioural Specifications .602 M.C. Molina, J.M. Mendias and R. Hermida 9A.2 Coupling-Aware High-level Interconnect Synthesis for Low Power .609 Chun-Gi Lyuh, Taewhan Kim and Ki-Wook Kim 9A.3 Layout-Driven Resource Sharing in High-Level Synthesis .614 Junhyung Urn, Jae-hoon Kim and Taewhan Kim Session 9B: Advances in Timing Analysis Accuracy Moderators: Tim Burks, Magma Design Automation, Inc., Cupertino, CA David Blaauw, University of Michigan, Ann Arbor, MI 9B.1 A Delay Metric for RC Circuits based on the Weibull Distribution .620 Frank їли, Chandramouli Kashyap and Charles J. Alpert 9B.2 WTA — Waveform-Based Tuning Analysis for Deep Submkron .625 Circuits Larry McMurchie and Carl Sechen 9B.3 General Framework for Removal of Clock Network Pessimism .632 Jindřich Zejda and Paid Frain xv Session 9C: Customization of Embedded System Architectures Moderators: Petru Eles, Linköping University, Linköping, Sweden Нігоуикі Tomiyama, ISIT, Fukuoka, Japan 9C.1 Synthesis of Custom Processors based on Extensible Platforms. 641 Fei Sun, Srivaths Ravi, Anand Ragunathan and Niraj K. Jha 9C.2 Efficient Instruction Encoding for Automatic Instruction Set Design.649 of Configurable ASIPs Jong-eun Lee, Kiyoung Choi and Nikil Dutt 9C.3 Synthesis of Customized Loop Caches for Core-Based Embedded .655 Systems Susan Cotterell and Frank Vahid 9C.4 A Hierarchical Modeling Framework for On-Chip Communication .663 Architectures Xinping Zhu and Sharad Malik Session 9D: Advances in Combinational Synthesis Moderators: Olivier Coudert, Monterey Design Systems, Inc., Sunnyvale, CA Prabhakar Kudva, IBM Corp., Yorktown Heights, NY 9D.1 A New Enhanced SPFD Rewiring Algorithm .672 Jason Cong, Joey Y. Lun and Wangning Long 9D.2 Topologically Constrained Logic Synthesis .679 Subarnarekha Sinha, Alan Mishchenko and Robert K. Brayton 9DJ Resynthesis of Multi-Level Circuits Under Tight Constraints Using .687 Symbolic Optimization Victor N. Kravets and Karem A. Sakallah 9D.4 Folding of Logic Functions and Its Application to Look Up Table .694 Compaction Shinji Kimura, Takashi Horiyama, Masaid Nakanishi and Hirotsugu Kajihara Session 10A: System-Level Performance and Power Modeling and Optimization Moderators: Frank Vahid, University of California, Riverside, CA Xiaobo (Sharon) Ни, University of Notre Dame, Notre Dame, IN 10A.1 SchedulabUity Analysis of Multiprocessor Real-Time Applications with. . 699 Stochastic Task Execution Times Sorin Manolache, Petru Eles and 7Љо Peng xvi 10А.2 Battery-Aware Power Management Based on Markovian Decision .707 Processes Peng Rong and Massoud Pedram 10A.3 Leakage Power Modeling and Reduction with Data Retention .714 Weiping Liao, Joseph M. Basile and Lei He Session 10B: Advances in Dynamic Voltage Scheduling Moderators: Rajesh K. Gupta, University of California, Irvine, С А Miodrag Potkonjak, University of California, Los Angeles, С А 10B.1 Combined Dynamic Voltage Scaling and Adaptive Body Biasing .721 for Lower Power Microprocessors under Dynamic Workloads Steven M. Martin, Krisztián Flautner, Trevor Mudge and David Blaauw 10B.2 A Realistic Variable Voltage Scheduling Model for Real-Time .726 Applications Bren Mochocki, Xiaobo (Sharon) Ни and Gang Quan 10B.3 Frame-Based Dynamic Voltage and Frequency Scaling for a MPEG .732 Decoder Kihwan Choi, Karthik Dantu, Wei-Chung Cheng and Massoud Pedram Session IOC: Techniques in Placement Moderators: Lukas P.P.P. Van Ginneken, Magma Design Automation, Inc., Cupertino, CA Kia Bazargan, University of Minnesota, Minneapolis, MN 10C.1 Congestion Minimization During Placement Without Estimation .739 Во Ни and Małgorzata Marek-Sadowska 10C.2 Free Space Management for Cut-Based Placement .746 Charles J. Alpert, Gi-Joon Nam and Paul G. Villarrubia 10C.3 Incremental Placement for Layout-Driven Optimizations on FPGAs .752 Deshanand P. Singh and Stephen D. Brown Session 10D: Model Order Reduction Moderators: Mustafa Celik, Magma Design Automation, Inc., Cupertino, CA Sharad Kapur, Agere Systems, Inc., Murray Hill, NJ 10D.1 Robust and Passive Model Order Reduction for Circuits Containing .761 Susceptance Elements Hui Zheng and Lawrence T. Pileggi xvu 10D.2 Efficient Model Order Reduction via Multi-Node Moment Matching .767 Yehea I. Ismail 10D.3 Optimization Based Passive Constrained Fitting .775 Carlos P. Coelho, Joel R. Phillips and Luis Miguel Silveira Session 11 A: Embedded Tutorial: SAT & ATPG: Boolean Engines for Formal Hardware Verification Moderators: Joao Marques-Silva, Technical University Lisbon, Lisboa, Portugal Karem A. SakaUah, University of Michigan, Ann Arbor, MI НАЛ SAT & ATPG: Boolean Engines for Formal Hardware Verification .782 Armin Biere and Wolfgang Kunz 11A.2 ATPG-based Logic Synthesis: An Overview .786 Chih-Wei Jim Chang and Małgorzata Marek-Sadowska Session 1 IB: Embedded Tutorial: The A to Z of SoCs Moderators: Grant E. Martin, Cadence Berkeley Labs., Berkeley, С А Kees Α. Vissers, Chameleon Systems, Inc., San Jose, С А 11B.1 The A to Z of SoCs .791 Reinaldo A. Bergamaschi and John Cohn XVIII
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discipline	Technik Informatik Maschinenbau
format	Conference Proceeding Book
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genre_facet	Konferenzschrift 2002 San Jose, Calif.
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isbn	0780376072
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spelling	International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 2002 San José, Calif. Verfasser (DE-588)10056622-4 aut ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2002 IEEE ACM digest of technical papers Proceedings of the 2002 International Conference on Computer-Aided Design Piscataway, NJ IEEE [u.a.] 2002 XXX, 798 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2002 San Jose, Calif. gnd-content CAD (DE-588)4069794-0 s DE-604 Institute of Electrical and Electronics Engineers Sonstige (DE-588)1692-5 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010297724&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] CAD (DE-588)4069794-0 gnd
subject_GND	(DE-588)4069794-0 (DE-588)1071861417
title	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
title_alt	IEEE ACM digest of technical papers Proceedings of the 2002 International Conference on Computer-Aided Design
title_auth	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
title_exact_search	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
title_full	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2002
title_fullStr	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2002
title_full_unstemmed	ICCAD 2002 November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers] IEEE/ACM International Conference on Computer Aided Design, ICCAD 2002
title_short	ICCAD 2002
title_sort	iccad 2002 november 10 14 2002 doubletree hotel san jose ca ieee acm digest of technical papers
title_sub	November 10 - 14, 2002, Doubletree Hotel, San Jose, CA ; [IEEE ACM digest of technical papers]
topic	CAD (DE-588)4069794-0 gnd
topic_facet	CAD Konferenzschrift 2002 San Jose, Calif.
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010297724&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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