Proceedings of ISPD '02: 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
ACM Press
2002
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 208 S. Ill., graph. Darst. |
| ISBN: | 1581134606 |
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Datensatz im Suchindex
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| adam_text | Table
of
Contents
Symposium
Organization List
...............................................................................................................viii
Keynote Address
Host: S. Sapatnekar (University of Minnesota)
Challenges and Principles of Physical Design (Invited Paper)
.............................................3
S. T.
Teig
(Simplex Solutions, Inc.)
Session
1:
Placement
Chair: F. Johannes
(TU
Munich)
An Effective Congestion Driven Placement Framework (Best Paper Awardee)
...............6
U. Brenner, A. Rohe (University of Bonn)
Consistent Placement of Macro-Blocks Using Floorplanning
and Standard-Cell Placement
.......................................................................................................12
S.
N.
Adya, I. L. Markov (University of Michigan)
Session
2:
Panel
-
Do you have to get your whole
physical solution from one company
..................................................................................19
Organizer and Moderator: D. Hill (Synopsys)
Panelists: R. Camposano (Synopsys); W-J. Dai (Silicon Perspective); P. Hersher (Simplex);
J. G.
Xi
(Plato); S. Young (Nassda)
Session
3:
Leakage Current
Chair: P. Groeneveld (Magma)
Leakage Current in Low Standby Power and High Performance Devices:
Trends and Challenges (Invited Paper)
.....................................................................................22
G. C.-F.
Yeap (Motorola Inc.)
Leakage-Tolerant Design Techniques for High Performance Processors
(Invited Paper)
..................................................................................................................................28
V. Oq (Intel Labs)
Session
4:
Physical Hierarchy
Chair: K. Bazargan (University of Minnesota)
Design Hierarchy Guided Multilevel Circuit Partitioning
......................................................30
Y
Cheon, D. F. Wong (The University of Texas at Austin)
Physical Hierarchy Generation with Routing Congestion Control
.....................................36
C.-C. Chang, J. Cong, X. Yuan (UCLA); Z. Pan (IBMT.J. Watson Research Center)
Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement
.....42
X. Yang, B.-K. Choi, M. Sarrafzadeh (University of California at Los Angeles)
Session
5:
Floorplanning and Post-Layout Optimization
Chair: H. Zhou (Northwestern)
Routability Driven Floorplanner with Buffer Block Planning
...............................................50
С
W. Sham,
E.
F. Y.
Young (The Chinese University of Hong Kong)
Integrated Floorplanning with Buffer/Channel Insertion
for Bus-Based Microprocessor Designs
...................................................................................56
F. Rafiq,
N.
Sherwani (Intel Microlectronics
Senïces); M.
Chrzanowska-
Jeske (Portland State University);
H. H.
Yang (Intel Corporation)
V
TEG: A
New Post-Layout Optimization Method
......................................................................62
S. Zhang, W. W.-M. Dai (University of California)
An Algorithm for Optimal Decoupling Capacitor Sizing and Placement
for Standard Cell Layouts
.............................................................................................................68
H. Su, S.
R. Nassif (IBMARL); S. S. Sapatnekar
(University of Minnesota)
Session
6:
Thermal Issues
Chair: M. Pedram (University of Southern California)
On-chip Thermal Engineering for Peta-scale Integration (Invited Paper)
........................76
S.-M. Kang (University of California, Santa Cruz)
Session
7:
Crosstalk Noise
Chair: M. Marek-Sadowska (University of California, Santa Barbara)
Shield Count Minimization in Congested Regions
.................................................................78
P. Saxena, S. Gupta (Intel Corporation)
On Convergence of Switching Windows Computation in Presence
of Crosstalk Noise
...........................................................................................................................84
P. Chen (University of California, Berkeley and Silicon Perspective); Y. Kukimoto,
C.-C.
Teng
(University of California, Berkeley); K. Keutzer (Silicon Perspective)
Session
8:
Buffer Insertion
Chair: J. Lou (Synopsys)
Buffer Insertion with Adaptive Blockage Avoidance
.............................................................92
J. Hu, S. T. Quay, G. Gandham (IBM Microelectronics);
С
J. Alpert (IBMARL)
Buffer Tree Synthesis with Consideration of Temporal Locality, Sink Polarity
Requirements, Solution Cost and Blockages
..........................................................................98
M. Hrkic. J. Lillis (University of Illinois at Chicago)
Simultaneous Driver Sizing and Buffer Insertion Using a Delay
Penalty Estimation Technique
....................................................................................................104
С
Alpert, J.
Ни, С
Kashyap, S. Quay, G. Gandham (IBM);
С
Chu
(Iowa State University);
M.
Hrkic (University of Illinois at Chicago)
Session
9:
Future Design Trends
Chair:
C. J.
Alpert (IBM)
A Roadmap and Visions for Physical Design (Invited Paper)
..........................................112
A. B. Kahng (University of California, San Diego)
Physical Design with Multiple On-Chip Voltages (Invited Paper)
.....................................118
C. Chen (University of Windsor)
Session
10:
Poster Paper Introductions
Chair: J. Lillis (University of Illinois at Chicago)
Incremental Delay Changes due to Crosstalk Noise
............................................................120
L. H. Chen
(Avant!
Corporation); M. Marek-Sadowska (University of California, Santa Barbara)
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
.....................................126
M. Hashimoto. M. Takaashi, H. Onodera (Kyoto University)
Understanding and Addressing the Impact of Wiring Congestion
During Technology Mapping
......................................................................................................131
D. Pandini (STMicroelectronics); L. T. Pileggi, A. J. Strojwas (Carnegie Mellon University)
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis
..............................137
Y. Chen (University of California, Los Angeles); A. B. Kahng (University of California, San Diego);
G. Robins (University of Virginia); A. Zelikovsky (Geoige State University)
Min-Max
Placement For Large Scale Timing Optimization
.................................................143
A. B. Kahng (University of California, San Diego); S. Mantik (University of California, Los Angeles);
1.
L. Markov (University of Michigan)
Global Clustering-Based Performance-Driven Circuit Partitioning
.................................149
J. Cong (University of California at Los Angeles);
С
Wu (Aphis Design Technologies, Inc.)
Net Criticality Revisited: An Effective Method to Improve Timing
in Physical Design
.........................................................................................................................155
H. Chang, E. Shragowitz, J. Liu (University of Minnesota); H. Youssef
(Universite du
Centre);
B.
Lu
(Cadence Design Systems Inc.); S. Sutanthavibul (Intel Corporation)
FAR: Fixed-Points Addition
&
Relaxation Based Placement
.............................................161
В. Ни, М.
Marek-Sadowska (University of California, Santa Barbara)
Session
11:
Design Above the Silicon Surface: Package, Board and Beyond
.......
1
67
Organizer and Moderator: R. A.
Rutenbar
(Carnegie Mellon University)
Speakers: B. McCredie (IBM); K. Rinebold
(Avant!);
D.
Wood (Intel)
Session
12:
Timing Closure
Chair: M. Pedram (University of Southern California)
Timing Closure Based on Physical Hierarchy (Invited Paper)
..........................................
1
70
J. Cong (University of California, Los Angeles)
Session
13:
Routing
Chair: I. Markov (University of Michigan)
Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation
.............................
1
76
S. Lee,
D. F.
Wong (University of Texas at Austin)
sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications
in Routing
........................................................................................................................................
1
82
H. Xu, R. A.
Rutenbar
(Carnegie Mellon University);
K. Sakallah
(University of Michigan)
Session
14:
Topics in Physical Design
Chair: L. Scheffer (Cadence)
Temporal Logic Replication for Dynamically
Reconfigurable
FPGA Partitioning 1
90
W.-K.
Мак
(University of South Florida); E. F. Y. Young (The Chinese University of Hong Kong)
Twin Binary Sequences: A Non-Redundant Representation
for General Non-Slicing Floorplan
............................................................................................
1
96
E. F. Y
Young (The Chinese University of Hong Kong);
С. С
N.
Chu.
Z.
С.
Shen
(¡owa Stare
University)
Geometrically Parameterized Interconnect Performance Models
for Interconnect Synthesis
..........................................................................................................202
L. Daniel (University of California, Berkeley);
C. S.
Ong.
S. C.
Low.
К.
H. Lee
(National University of Singapore
);
J. White (Massachusetts Institute of Technology)
Author Index
........................................................................................................................................208
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| spelling | International Symposium on Physical Design 6 2002 Del Mar, Calif. Verfasser (DE-588)10055488-X aut Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 New York, NY ACM Press 2002 VIII, 208 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Very large scale integration Congresses VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2002 Del Mar Calif. gnd-content VLSI (DE-588)4117388-0 s CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010290785&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 Integrated circuits Very large scale integration Congresses VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| title_auth | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| title_exact_search | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| title_full | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| title_fullStr | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| title_full_unstemmed | Proceedings of ISPD '02 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| title_short | Proceedings of ISPD '02 |
| title_sort | proceedings of ispd 02 2002 international symposium on physical design hilton san diego del mar del mar california usa april 7 10 2002 |
| title_sub | 2002 International Symposium on Physical Design ; Hilton San Diego Del Mar, Del Mar, California, USA, April 7 - 10, 2002 |
| topic | Integrated circuits Very large scale integration Congresses VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Integrated circuits Very large scale integration Congresses VLSI CAD Konferenzschrift 2002 Del Mar Calif. |
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