FPGA: ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003
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| Format: | Conference Proceeding Book |
| Language: | Undetermined |
| Published: |
New York, NY
Assoc. for Computing Machinery
2003
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | VII, 249 S. Ill., graph. Darst. |
| ISBN: | 158113651X |
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MARC
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| adam_text | Table
of
Contents
Session
1 :
Novel
Architectures
Chair:
Michael Butts
(Cadence)
•
Architectures and Algorithms for Synthesizable Embedded
Programmable Logic
Cores
...............3
N.
Kafafi, K. Bozman, S. J. E.
Wilton (University of British
Columbia)
•
The
Stratix™
Routing and Logic Architecture
...............................................................................................12
D. Lewis, V. Betz, P. Laventis. S. Marquardt, J. Rose
(Altera
Toronto Technology Centre), D. Jefferson, A. Lee.
С
Lane,
С
McClintock, B. Pedersen, G. Powell, S. Reddy,
С
Wysocki. R.
СШ
(Altera
Corporation)
•
A Pipelined Configurable Gate Array for Embedded Processors
...........................................................21
A. Lodi. M.
Toma,
F.
Campi, A. Cappelli, R. Guerrieri
(University of
Bologna),
R.
Canegallo
(ST
Microelectronics CR&D)
Session
2:
Placement
Chair: Vaughn Betz
(Altera
Corporation)
•
Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement
.....................33
M. G. Wrighton. A. M. DeHon (California Institute of Technology)
•
Parallel Placement for Field-Programmable Gate Arrays
..........................................................................43
P. K. Chan, M. D.
F. Schlag
(University of California. Santa Cruz)
•
I/O Placement for FPGAs with Multiple I/O Standards
................................................................................51
W.-K.
Mak
(University of South Florida)
Session
3:
Routing
Chair: Jason Cong (University of California, Los Angeles)
•
Wire Type Assignment for FPGA Routing
......................................................................................................61
S. Lee (University of Texas at Austin), H. Xiang, D. F. Wong (University of Illinois. Urhana-Champaign),
R. Y. Sun f
Minx Inc.)
•
PipeRoute: A Pipelining-Aware Router for FPGAs
......................................................................................68
A. Sharma,
С
Ebeling. S. Hauck (University o/H ashington)
•
Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes
.........................................................78
R. Huans. J. Wawrzvnek (University of California. Berkeley), A. DeHon (California Institute of I
etimologi
Session
4:
Prototyping, Verification, and Test
Chair: Majid Sarrafzadeh (University of California. Los Angeles)
•
Implementation of BEE: a Real-Time Large-scale Hardware Emulation Engine
.................................91
C. Chang. B. Richards.
R. W.
Brodersen (University of California. Berkeley).
K. Kuusilinna (University of California, Berkeley and Tampere University of Technology
ι
High-Levei Modeling and FPGA Prototyping of Microprocessors
........................................................100
J. Ray (Advanced Micro Devices, Inc.), J.
С. Ное
(Carnegie Mellon University)
Reducing Pin and Area Overhead in Fault-Tolerant FPGA-based Designs
108
F. Lima. L.
Carro,
R.
Reis (Universidade Federal do Rio Grande do Sul)
Panei
Attack of the Killer Gate Arrays
......................................................................................................................
Н8
Moderator: Michael Butts (Cadence)
Session
5:
Logic Synthesis and Mapping
Chair: Steve Wilton, (University of British Columbia)
•
Placement-Driven Technology Mapping for LUT-Based FPGAs
...........................................................121
J. Y. Lin (Aphis Design Technologies, Inc.), A. Jagannathan, J. Cong (University of California, Los Angeles)
•
Verifying the Correctness of FPGA Logic Synthesis Algorithms
..........................................................127
B. Ratchev, M. Hutton, G. Baeckler, B. van
Antwerpen
(Altera
Corporation)
•
Using Logic Duplication to Improve Performance in FPGAs
..................................................................136
K. Schabas, S. D. Brown (University of Toronto)
Session
6:
Device-Level Design
Chair: Guy Lemieux, (University of British Columbia)
•
A Scalable
2
V,
20
GHz FPGA using SiGe HBT BiCMOS Technology
..................................................145
J. R. Guo,
С
You. K. Zhou. R. P. Kraft, J. F. McDonald (Rensselaer Polytechnic Institute),
B. S.
Goda
(UnitedStates Military Academy)
•
Design of FPGA Interconnect for Multilevel Metalization
.........................................................................154
R. Rubin. A. DeHon (California Institute of Technology)
•
Automatic Transistor and Physical Design of FPGA Tiles from an Architectural Specification
. 164
K. Padalia, R. Fung, M. Bourgeauh, A. Egier, J. Rose (University of Toronto)
Session
7:
Architecture Analysis and Automation
Chair: Sinan Kaptanoglu.
(Altera
Corporation)
•
Architecture Evaluation for Power-Efficient FPGAs
..................................................................................175
F. Li. D. Chen. L. He. J. Cong (University of California. Los Angeles)
•
Post-Placement
С
-slow Retiming for the Xilinx Virtex FPGA
.................................................................185
N.
Weaver. Y. Markovskiy. Y.
Patel,
J. W:awrzynek (University of California, Berkeley)
•
An FPGA Architecture with Enhanced Datapath Functionality
..............................................................195
K. Leijten-Nowak (Eindhoven University of Technology), J. L. van
Meerbergen
(Philips Research Labs)
Session 8: Applications
Chair:
Ray Andraka, (Andraka Consulting Group)
•
A Fully Pipelined
Memoryless 17.8
Gbps
AES-128 Encryptor................................................................207
K. U.
Järvinen,
M. T. Tommiska.
J. O. Skyítä
(Helsinki
University of Technology)
•
A Methodology to Implement Block Ciphers in
Reconfigurable
Hardware
and its Application to Fast and Compact AES RIJNDAEL
.......................................................................
216
F.-X. Standaert, G. Rouvroy, J.-J. Quisquater, J.-D.
Legat
(Université Catholique de
Louvam)
•
Energy-Efficient Signal Processing Using FPGAs
.....................................................................................225
S. Choi, R. Scrofano, V. K. Prasanna (University of Southern California). J.-W. Jang (Sogang University)
Posters
•
Poster Abstracts
...................................................................................................................................................237
(Alphabetically by Lead Author)
Author Index
.............................................................................................................................................................249
|
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| author_facet | FPGA Monterey, Calif |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T19:12:30Z |
| institution | BVB |
| institution_GND | (DE-588)1902682-1 |
| isbn | 158113651X |
| language | Undetermined |
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| physical | VII, 249 S. Ill., graph. Darst. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Assoc. for Computing Machinery |
| record_format | marc |
| spelling | FPGA 11 2003 Monterey, Calif. Verfasser (DE-588)1902682-1 aut FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 FPGA 2003 New York, NY Assoc. for Computing Machinery 2003 VII, 249 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Field programmable gate array (DE-588)4347749-5 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2003 Monterey Calif. gnd-content Field programmable gate array (DE-588)4347749-5 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010257460&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)1071861417 |
| title | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| title_alt | FPGA 2003 |
| title_auth | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| title_exact_search | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| title_full | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| title_fullStr | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| title_full_unstemmed | FPGA ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| title_short | FPGA |
| title_sort | fpga acm sigda eleventh acm international symposium on field programmable gate arrays monterey beach hotel monterey california usa february 23 25 2003 |
| title_sub | ACM SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA, February 23 - 25, 2003 |
| topic | Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Field programmable gate array Konferenzschrift 2003 Monterey Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010257460&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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