International Symposium on System Synthesis: 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
ACM Press
2002
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | X, 268 S. Ill., graph. Darst. |
| ISBN: | 1581135769 |
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Datensatz im Suchindex
| _version_ | 1820868165120294912 |
|---|---|
| adam_text |
Table
of
Contents
ISSS'02
Conference Organization
.
viii
Reviewers
.ix
ISSS'02 Sponsors
&
Supporters
.
χ
9:00-10:00 ·
Session
1:
Keynote
•
Mobile, Broadband, Ubiquitous, and the Information Renaissance
.1
K. Ohboshi (NTT DoCoMo, Inc.)
10:20-12:00 ·
Session
2:
Processor-Based System
•
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs
with Coarse Grain Functional Units
.2
B. Middha, V. Raj, A.
Gangwar,
A. Kumar, M. Balakrishnan (Indian Institute of Technology),
P.
lenne
(Swiss Federal Institute of Technology Lausanne (EPFL)
•
Tuning of Loop Cache Architectures to Programs in Embedded System Design
.8
S. Cotterell (University of California, Riverside),
F. Vahid (University of California, Riverside and Center for Embedded Computer Systems)
•
Combined Functional Partitioning and Communication Speed Selection for
Networked Voltage-Scalable Processors
.14
J. Liu, P.
H. Chou,
N.
Bagherzadeh (University of California, Irvine)
•
Optimal Message-Passing for Data Coherency in Distributed Architecture
.20
J. Peng, D. Gajski (University of California, Irvine)
•
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
.26
F. Gharsalli, D. Lyonnard, S. Meftali, F. Rousseau, A. A. Jerraya
(Laboratoire
ΏΜΑ)
•
An Accelerated Datapath Width Optimization Scheme for Area Reduction
of Embedded Systems
.32
M. M. Uddin,
Y. Cao,
H.
Yasuura (Kyushu University)
13:40-14:40 ·
Session
3:
Reconfigurable
System
•
Datapath Merging and Interconnection Sharing for
Reconfigurable
Architectures
.38
N.
Moreano (DCT-UFMS andIC-UNICAMP), G.
Araújo
(IC-UNICAMP), Z. Huang, S. Malik (Princeton University)
•
A Run-Time Word-Level
Reconfigurable
Coarse-Grain
Functional Unit for a VLIW Processor
.44
N.
G.
Busa
(Philips Research Laboratories), C. R.
Sala
(Sony
Espana
S.A.
Design Division)
•
Energy/Power Estimation of Regular Processor Arrays
.50
S. Derrien
(IRISA), S.
Rajopadhye (Colorado State University)
•
Controller Estimation for FPGA Target Architectures During High-Level Synthesis
.56
С
Menn, O.
Bringmann
(FZI
Forschungszentrum Informatik), W. Rosenstiel (Universität Tübingen)
14:40-15:50 · Session 4:
Practical
Experiences
•
System-Level Modeling of a Network Switch SoC
.62
J. M. Paul, C. P. Andrews, A. S. Cassidy, D. E. Thomas (Carnegie Mellon University)
•
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
.68
E.
A. de Kock
(Philips Research)
•
System-Level Design of IEEE1394 Bus Segment Bridge
.74
H. Yamamoto, K. Chikamura, A. Shigiya, K. Tsujino, T.
Izumi,
T. Onoye, Y. Nakamura
(Kyoto University)
•
Security-Driven Exploration of Cryptography in DSP Cores
.80
С
H. Gebotys
(University of Waterloo)
•
A Case Study of Hardware and Software Synthesis in ForSyDe
.86
Z.
Lu,
I. Sander, A. Jantsch (Royal Institute of Technology)
16:30-17:50 ·
Session
5:
Special Session on On-Chip Multi-Processing
Organizers: Ahmed A. Jeraya
(TIMA
Laboratory), Wayne Wolf (Princeton University)
•
An Adaptive Low-power Transmission Scheme for On-chip Networks
.92
F. Worm, P.
lenne,
P. Thiran (Swiss Federal Institute of Technology Lausanne (EPFL),
G.
De Micheli
(Stanford University)
•
CMP on SoC: Architect's View
.101
S. Sakai (The University of Tokyo)
•
Design Experience of a Chip Multiprocessor Merlot and Expectation
to Functional Verification
.103
S. Matsushita (NEC Corporation)
•
OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip
Multiprocessors
.109
M. Sato (University of Tsukuba)
8:50-10:05 ·
Session
6:
Invited Talk
•
Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems
.112
P. Yang, P.
Marchai,
С.
Wong,
S.
Himpe, F. Catthoor,
P.
David,
J.
Vounckx,
R.
Lauwereins
(K. U.
Leuven-ESAT)
10:20-12:00 · Session 7: Design
Methodologies
Basedon
Instruction Code
•
A
Design Space
Exploration
Framework
for Reduced Bit-width Instruction
Set Architecture (rlSA) Design
.120
A. Halambi, A. Shrivastava, P. Biswas,
N.
Dutt, A.
Nicolau
(University of California at Irvine)
•
Timing Analysis of Embedded Software for Speculative Processors
.126
T.
Mitra,
A. Roychoudhury, X. Li (National University of Singapore)
•
Modeling Assembly Instruction Timing in Superscalar Architectures
.132
G. Beltrame (CEFRIEL Research Centre),
С
Brandolese, W. Fornaciari, F.
Salice,
D.
Sciuto, V. Trianni
(Politecnico di Milano)
•
Code Compression for VLIW Processors Using Variable-to-fixed Coding
.138
Y. Xie, W. Wolf (Princeton University), H. Lekatsas (NEC USA)
•
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
.144
Q. Zhuge, B. Xiao,
Z. Shao, E. H.-M.
Sha
(University of Texas at Dallas),
C. Chantrapomchai (Silpakorn University)
13:40-15:40 · Session 8: Simulation
and Verification
• The Formal
Execution Semantics of SpecC
.150
W.
Mueller
(Paderborn
University),
R.
Dömer, A.
Gerstlauer
(University of
California
at Irvine)
•
Formal Verification in a Component-based Reuse Methodology
.156
D.
Karlsson,
P.
Eles,
Ζ.
Peng
(Linköpings Universitet)
•
Validation in a Component-Based Design Flow for Multicore SoCs
.162
G. Nicolescu, S. Yoo, A. Bouchhima, A. A. Jerraya
(ΤΊΜΑ
Laboratory)
•
Efficient Simulation of Synthesis-Oriented System Level Designs
.168
N.
Savoiu, S. K. Shukla, R. K. Gupta (University of California, Irvine)
•
Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs
.174
D. Kim, C.-E. Rhee, Y. Yi, S. Kim, H. Jung, S. Ha (Seoul National University)
•
A New Performance Evaluation Approach for System Level Design Space Exploration
.180
C. P. Joshi, A. Kumar, M. Balakrishnan (Indian Institute of Technology)
•
A Visual Approach to Validating System Level Designs
.186
J.
Klose
(University of Oldenburg), T.
Kropt
J.
Ruí
(University of
Tübingen)
16:20-17:40 ·
Session
9:
Special Session on Security on SoC
Organizers: Catherine H. Gebotys (University of Waterloo), Hiroto Yasuura (Kyushu University)
•
Special Session: Security on SoC
.192
C. Gebotys (University of Waterloo), H. Yasuura (Kyushu University),
M. Torla (Motorola), S. Ravi (NEC),
N.
Takagi (Nagoya University)
•
Securing Wireless Data: System Architecture Challenges
.195
S. Ravi, A. Raghunathan,
N.
Potlapally (NEC USA)
9:00-10:20 ·
Session
10:
Low Power Memory System
•
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems
.201
Y. Cao
(Kyushu University), H. Tomiyama (Institute of Systems
&
Information Technologies/KYUSHU),
T. Okuma, H. Yasuura (Kyushu University)
•
Efficient Power Reduction Techniques for Time Multiplexed Address Buses
.207
M. Mamidipaka,
N. Dutt, D. Hirschberg
(University of California, Irvine)
•
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory
.213
S. Steinke,
N.
Grunwald, L.
Wehmeyer
(University of Dortmund),
R. Banakar, M. Balakrishnan (Indian Institute of Technology), P. Marwedel (University of Dortmund)
•
Low-power Data Memory Communication for Application-Specific Embedded Processors
.219
P.
Petrov,
A. Orailoglu (University of California, San Diego)
•
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage
and Frequency Scaling of Off-Chip Buses and Memory
.225
K. Puttaswamy, K.-W. Choi, J. C. Park, V. J. Mooney
ΙΠ,
A. Chatterjee (Georgia Institute of Technology),
P. Ellervee (Tallinn Technical University)
10:50-12:20 ·
Session
11:
High Level and Architectural Synthesis
•
System-Level Abstraction Semantics
.231
A.
Gerstlauer,
D. D. Gajski
(University of California at Irvine)
•
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
.237
G. Cabodi
(Politécnico
di
Torino),
M.
Lazarescu
(Cadence Design Systems, Inc.),
L. Lavagno,
S.
Nocco,
С.
Passerone, S. Quer
(Politecnico di Torino)
• Round-robin Arbiter
Design and
Generation.243
E. S.
Shin,
V. J.
Mooney
ΠΙ,
G.
F. Riley (Georgia Institute
of
Technology)
• An Object-Oriented Design
Process for
System-on-Chip
using UML
.249
Q.
Zhu,
A. Matsuda, S. Kuwamura, T.
Nakata
(Fujitsu Laboratories Limited), M. Shoji (Fujitsu Limited)
•
Improving Embedded
System Design
by Means of HW-SW
Compilation
on Reconfigurable
Coprocessors
.255
J.
M.
Moya
(Technical University of Madrid), F.
Rincón,
F.
Moya,
J. C.
López
(University of
Castilla-La Mancha)
•
Dynamic Common Sub-Expression Elimination during Scheduling
in High-Level Synthesis
.261
S. Gupta, M. Reshadi,
N.
Savoiu,
N. Dutt, R.
Gupta, A.
Nicolau
(University of California at Irvine)
Author Index
.267 |
| any_adam_object | 1 |
| author_corporate | International Symposium on System Synthesis Kyōto |
| author_corporate_role | aut |
| author_facet | International Symposium on System Synthesis Kyōto |
| author_sort | International Symposium on System Synthesis Kyōto |
| building | Verbundindex |
| bvnumber | BV014802549 |
| classification_rvk | SS 2002 |
| classification_tum | DAT 060f |
| ctrlnum | (OCoLC)633486417 (DE-599)BVBBV014802549 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| indexdate | 2025-01-10T13:20:02Z |
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| physical | X, 268 S. Ill., graph. Darst. |
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| publisher | ACM Press |
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| spelling | International Symposium on System Synthesis 15 2002 Kyōto Verfasser (DE-588)10058881-5 aut International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 ISSS 2002 ISSS'02 Proceedings New York, NY ACM Press 2002 X, 268 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung (DE-588)4011152-0 gnd rswk-swf Systemsynthese (DE-588)4198909-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2002 Kioto gnd-content Systemsynthese (DE-588)4198909-0 s Datenverarbeitung (DE-588)4011152-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=010017352&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 Datenverarbeitung (DE-588)4011152-0 gnd Systemsynthese (DE-588)4198909-0 gnd |
| subject_GND | (DE-588)4011152-0 (DE-588)4198909-0 (DE-588)1071861417 |
| title | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| title_alt | ISSS 2002 ISSS'02 Proceedings |
| title_auth | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| title_exact_search | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| title_full | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| title_fullStr | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| title_full_unstemmed | International Symposium on System Synthesis 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| title_short | International Symposium on System Synthesis |
| title_sort | international symposium on system synthesis 15th isss kyoto japan october 2 4 2002 |
| title_sub | 15th ISSS ; Kyoto, Japan, October 2 - 4, 2002 |
| topic | Datenverarbeitung (DE-588)4011152-0 gnd Systemsynthese (DE-588)4198909-0 gnd |
| topic_facet | Datenverarbeitung Systemsynthese Konferenzschrift 2002 Kioto |
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