Rechnerarchitektur: Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | German |
| Veröffentlicht: |
Braunschweig [u.a.]
Vieweg
2002
|
| Ausgabe: | 3., vollst. aktualisierte und erw. Aufl. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XVII, 430 S. Ill., graph. Darst. |
| ISBN: | 3528255986 |
Internformat
MARC
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| 100 | 1 | |a Herrmann, Paul |e Verfasser |0 (DE-588)1024045072 |4 aut | |
| 245 | 1 | 0 | |a Rechnerarchitektur |b Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner |c Paul Herrmann |
| 250 | |a 3., vollst. aktualisierte und erw. Aufl. | ||
| 264 | 1 | |a Braunschweig [u.a.] |b Vieweg |c 2002 | |
| 300 | |a XVII, 430 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4123623-3 |a Lehrbuch |2 gnd-content | |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-009950919 | ||
Datensatz im Suchindex
| DE-BY-863_location | 1000 |
|---|---|
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| adam_text | Inhalt
1 Einführung....................................................................................................1
1.1 Allgemeine Einführung............................................................................................1
1.2 Rechnerarchitektur-Begriff......................................................................................4
1.3 Definitionen...............................................................................................................6
1.4 Software-Architektur................................................................................................6
1.5 Hardware-Architektur..............................................................................................8
1.6 Prinzipieller Rechneraufbau....................................................................................9
1.7 Hardware-Kosten eines Rechnersystems............................................................12
1.8 Wichtige Kenngrößen einer Rechnerarchitektur...............................................13
2 Technologische Grundlagen.......................................................................15
2.1 Einführung...............................................................................................................15
2.2 Integration in der Chip-Technologie...................................................................15
2.3 Prozessor-Design und Hardware-Implementierung.........................................19
2.4 Energieprobleme in Rechnersystemen................................................................27
2.5 SOI-Technologie.....................................................................................................34
3 Einfachst-Rechner.......................................................................................37
3.1 Einführung...............................................................................................................37
3.2 Architektur-Entscheidungen.................................................................................37
3.3 Funktions-Einheiten...............................................................................................38
3.3.1 Logische Einheit.............................................................................................38
3.3.2 Steuerung der ALU.........................................................................................39
3.3.3 Die Register.....................................................................................................40
3.3.3.1 Funktion der Register................................................................................40
3.3.3.2 Register-Implementierung.........................................................................41
3.3.4
Multiplexer
.......................................................................................................45
3.3.5 Der Hauptspeicher.........................................................................................45
3.3.6 Bussystem........................................................................................................47
3.3.7 Ablaufsteuerung..............................................................................................49
3.3.8 Das Leitwerk....................................................................................................53
3.3.9 Ein-und Ausgabe-Einheit.............................................................................57
3.3.10 Unterschiede zu realen Rechner-Implementierungen..............................59
XI
4 Adressierung................................................................................................65
4.1 Einführung...............................................................................................................65
4.2 Universakegister-Maschinen.................................................................................66
4.3 Byte
Ordering
..........................................................................................................68
4.4 Befehlsarten.............................................................................................................72
4.5 Registersatz der Zentraleinheit.............................................................................72
4.6 Befehlsformat und
Adressierungs
arten..............................................................73
4.7 64 Bit-Architekturen..............................................................................................75
5 Speichernutzung..........................................................................................79
5.1 Einführung..............................................................................................................79
5.2 Aufteilung des Hauptspeichers............................................................................80
5.3 Speicherschutz........................................................................................................82
5.4 Multitasking und Multiprogrammierung............................................................83
5.4.1 Multitasking.....................................................................................................83
5.4.2 Multiprogrammierung...................................................................................84
5.4.3 Speicherschutz in multiprogrammierten Betriebssystemen....................85
5.4.4 Speicherzerstückelung...................................................................................90
5.4.5 Overlay-Technik.............................................................................................91
6 Virtuelle Speicher.........................................................................................93
6.1 Einführung..............................................................................................................93
6.2 Virtueüer und realer Adressraum.........................................................................93
6.3 Adressumsetzung....................................................................................................94
6.4
Demand Paging.......................................................................................................
99
6.5 Prozessverwaltung................................................................................................102
6.5.1 Einfache virtuelle Speicher.........................................................................102
6.5.2 Mehrfacher virtueller Speicher...................................................................103
6.5.2.1 DEC VAX-Architektur...........................................................................104
6.5.2.2 IBM /390-Architektur............................................................................109
6.5.2.3 Motorola-IBM-Architekturen................................................................112
6.5.3 Seitengrößen..................................................................................................116
6.6 Lokalitäts-Prinzip.................................................................................................118
6.7 Seiten-Attribute.....................................................................................................120
6.8 Adressumsetzpuffer.............................................................................................121
XII
6.8.1 VoR-assoziativer
Adres
sums
etzpuf
fer
......................................................123
6.8.1.1 Aufbau und Funktionsweise..................................................................123
6.8.1.2 Adressumsetzpuffer-Ersetzungs-Algorithmen....................................126
6.8.2 Set-assoziativer
Adres
sums etzpuf
f
er.........................................................130
6.9 Der externe Seitenspeicher..................................................................................135
7 Virtuelle Speicherverwaltung in Multiprogrammsystemen.......................141
7.1 Funktionsweise......................................................................................................141
7.2 Gemeinsame Seitentafel verschiedener Prozesse............................................143
7.3 Ein- /Ausgabe-Operationen...............................................................................144
8 Segmentierung............................................................................................147
8.1 Einführung.............................................................................................................147
8.2 IBM RS/6000 Segmentierung.............................................................................149
8.3 IBM ESA/370 (/390) Segmentierung...............................................................150
8.4 Segmentierung der Intel-Architekturen.............................................................151
9 Hauptspeicher............................................................................................155
9.1 Hauptspeicher-Technologien..............................................................................155
9.2 Implementierungsarten einer Speicherzelle......................................................158
9.2.1 Statische Speicherzelle..................................................................................158
9.2.2 Dynamische Speicherzelle...........................................................................159
9.2.2.1 Funktionsweise.........................................................................................159
9.2.2.2 Fehlererkennung und
-korrektur
............................................................160
9.2.2.3 Zuverlässigkeit und Fehler-Codes.........................................................162
9.3 Adressierung des Hauptspeichers......................................................................169
9.4 Preisgestaltung von Hauptspeicher-Chips........................................................173
9.5 Erweiterungsspeicher
(expanded storage).........................................................
175
9.6
Extended Refresh Devices
..................................................................................179
9.7 Techniken zur Beschleunigung der Hauptspeicherzugriffe...........................180
9.7.1 Einführung.....................................................................................................180
9.7.2 Speicherverschachtelung (Memory
Interleaving)
....................................181
9.7.3 Cache-Speicher..............................................................................................183
9.7.3.1 Technologie...............................................................................................183
9.7.3.2 Cache-Prinzip............................................................................................184
XIII
9.7.3.3
Cache
ohne virtueUe Speichertechnik...................................................185
9.7.3.4 Leistungsfähigkeit des Cache-Speichers................................................195
9.7.3.5 Datengültigkeit.........................................................................................199
9.7.3.6 Nachladen des Cache..............................................................................201
9.7.3.7 Ll -, LZ-Cache..........................................................................................204
9.7.3.8 Cache mit virtueller Speichertechnik....................................................206
9.7.4
Prefetch-Buffer
.............................................................................................207
9.7.5 Pro und Kontra Havard-Architektur........................................................207
10 Mikroprogtammierang...........................................................................209
10.1 Horizontale Mikroprogramme...........................................................................213
10.2 Vertikale Mikroprogramme................................................................................214
10.3 Adressierung mittels Statusinformation............................................................215
10.4 Zweistufige Mikroprogramme............................................................................216
10.5 High Level Microcode.........................................................................................218
11 Pipelines..................................................................................................221
11.1 Einführung............................................................................................................221
11.2 Daten- und Steuerfluss........................................................................................223
11.2.1 Datenflusskonflikt........................................................................................225
11.2.2 Steuerflusskonflikt........................................................................................227
11.2.2.1
Delayed Branch....................................................................................
228
11.2.2.2
Branch Prediction
................................................................................229
11.2.2.3
Branch History Table
..........................................................................230
11.3
PipeHne-Speedup
..................................................................................................232
12
RISC-Atchitektur
....................................................................................235
12.1 Einführung............................................................................................................235
12.2 Theoretische Eigenschaften von RISC-Architekturen...................................236
12.3 Praktische Merkmale moderner RISC-Implementierungen..........................238
12.4 Moderne RISC-Architekturen............................................................................239
12.5 RISC-Identifikation..............................................................................................244
12.6 Swing-Architekturen............................................................................................245
13 Leistungsverhalten von Rechnern..........................................................247
13.1 Einführung............................................................................................................247
XIV
13.2 CPU-Leistung........................................................................................................247
13.3 Hauptspeicher-Effizienz.....................................................................................250
13.4 E/A-Leistung.........................................................................................................253
13.5 Benchmark.............................................................................................................255
13.5.1 Einführung.....................................................................................................255
13.5.2
Whetstone-Benchmark
................................................................................255
13.5.3 Dhrystone......................................................................................................256
13.5.4 Iinpack...........................................................................................................257
13.5.5 SPEC-Benchmarks.......................................................................................257
13.5.6 TPC-Benchmarks.........................................................................................258
13.5.7
Hard-
und Software-Monitore....................................................................260
14 Supetskalaie Architekturen.....................................................................261
14.1 Einführung.............................................................................................................261
14.2 Superskalare Architekturen..................................................................................263
14.2.1 Intel Pentium.................................................................................................266
14.3
Superpipelining
......................................................................................................268
14.3.1 DEC Alpha....................................................................................................270
14.3.2 Intel 80860.....................................................................................................271
14.3.3 IBMRS/6000................................................................................................277
14.4 VLIW-Architekturen............................................................................................282
15 Dynamic
Execution
................................................................................287
15.1 Einführung.............................................................................................................287
15.2 PentiumPro...........................................................................................................287
15.2.1
Рб
-Branch
Prediction
...................................................................................291
15.2.2 Mittlerer Teil der
Рб
-Pipeline
.....................................................................294
15.2.2.1
Speculative Execution..........................................................................
296
15.2.2.2 Register
Renaming
...............................................................................296
15.2.2.3
Out of
Order
Execution
.....................................................................297
15.2.3
Reservation Station
.......................................................................................299
15.2.4
Memory Reorder Buffer
..............................................................................300
15.3
Рб
-kompatible
Rechnerarchitekturen................................................................301
15.4
Pentium
4...............................................................................................................303
15.4.1
Trace-Cache
...................................................................................................304
XV
15.4.2 Die Pipeline...................................................................................................305
15.4.3
Rapid Execution Engine
..............................................................................309
15.5 Entwicklungs-Tendenzen....................................................................................309
16
Reale
64 Bit-Architekturen......................................................................311
16.1
IA-64
.......................................................................................................................311
16.1.1 Befehlsformat...............................................................................................314
16.1.2
Assembler-Format
.......................................................................................318
16.1.3
Predication
.....................................................................................................319
16.1.4
Control Speculation
.....................................................................................323
16.1.5
Data Speculation
..........................................................................................325
16.1.6
Software Pipelining
......................................................................................327
16.1.7
Register
der IA-64-Architektur..................................................................331
16.1.8
Register Stack
................................................................................................333
16.1.9 Itanium-Implementierung...........................................................................336
16.2
X86-64
und der
AMD Hammer
........................................................................338
16.3
MIPS64
...................................................................................................................340
16.3.1 1^864^^11^^....................................................................................340
16.3.2
5Kf
..................................................................................................................340
16.3.3
20Kc
...............................................................................................................341
16.4
Sun Ultra Sparc III
...............................................................................................342
16.5
IBM Power
4.........................................................................................................344
17
Vektorrechner
..........................................................................................347
17.1 Einführung............................................................................................................347
17.2
CDC CYBER
205................................................................................................349
17.3 Cache-Speicher......................................................................................................354
17.4
Register
...................................................................................................................355
17.4.1 Steuerregister.................................................................................................355
17.4.2
Vektorregister...............................................................................................
356
17.5 CRAY-Vektorrechner..........................................................................................357
17.6 Leistung von Vektorrechnern............................................................................360
17.7 Entwicklungs-Trends...........................................................................................362
18 Hardware-Komponenten zur Unterstützung des Betriebssystems........365
18.1 Einführung............................................................................................................365
XVI
18.2 Privilegstufen.........................................................................................................365
18.3 Stapel......................................................................................................................368
18.4 Unterbrechungen..................................................................................................374
19 Ein- und Ausgabe-Organisation.............................................................381
19.1 Einführung.............................................................................................................381
19.2 Plattenspeicher.......................................................................................................382
19.2.1 Magnetische Plattenspeicher.......................................................................382
19.2.2 Optische Plattenspeicher.............................................................................384
19.2.3 Holographische Speicher.............................................................................386
19.3 Festplattenspeicher-Ansteuerung.......................................................................386
19.4 EinVAusgabe-Befehle.........................................................................................389
19.5 Arten
det
Ein-/Ausgabe......................................................................................390
20 Patallelrechner........................................................................................393
20.1 Einführung.............................................................................................................393
20.2 Klassifizierung.......................................................................................................394
20.2.1
Tightly coupled MIMD-Architekturen
.....................................................395
20.2.2
Loosely coupled
MIMD-Architekturen....................................................400
20.3 Leistung von Parallelrechnern.............................................................................408
20.4 Datenabhängigkeit................................................................................................410
21 Multimedia-Rechnet...............................................................................413
21.1 Einführung.............................................................................................................413
21.2 Multimediale Datenverarbeitung........................................................................413
21.3 Multimedia-Erweiterungen..................................................................................415
21.3.1 SIMD..............................................................................................................416
21.3.2
MMX
..............................................................................................................417
21.3.3 SSE..................................................................................................................417
21.3.4 SSE2................................................................................................................418
XVII
|
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| illustrated | Illustrated |
| indexdate | 2025-02-20T06:44:37Z |
| institution | BVB |
| isbn | 3528255986 |
| language | German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009950919 |
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| owner | DE-20 DE-863 DE-BY-FWS DE-824 DE-573 DE-861 DE-29T DE-Aug4 DE-M347 DE-91G DE-BY-TUM DE-521 DE-858 DE-634 DE-83 DE-11 DE-355 DE-BY-UBR DE-2070s |
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| physical | XVII, 430 S. Ill., graph. Darst. |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | Vieweg |
| record_format | marc |
| spellingShingle | Herrmann, Paul Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4123623-3 |
| title | Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner |
| title_auth | Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner |
| title_exact_search | Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner |
| title_full | Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner Paul Herrmann |
| title_fullStr | Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner Paul Herrmann |
| title_full_unstemmed | Rechnerarchitektur Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner Paul Herrmann |
| title_short | Rechnerarchitektur |
| title_sort | rechnerarchitektur aufbau organisation und implementierung inklusive 64 bit technologie und parallelrechner |
| title_sub | Aufbau, Organisation und Implementierung, inklusive 64-Bit-Technologie und Parallelrechner |
| topic | Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Computerarchitektur Lehrbuch |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009950919&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT herrmannpaul rechnerarchitekturaufbauorganisationundimplementierunginklusive64bittechnologieundparallelrechner |
Inhaltsverzeichnis
THWS Würzburg Zentralbibliothek Lesesaal
| Signatur: |
1000 ST 150 H568(3) |
|---|---|
| Exemplar 1 | ausleihbar Checked out – Rückgabe bis: 30.04.2025 Vormerken |