Proceedings 2002: Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
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New York, NY
ACM Press
2002
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXXVI, 919 S. Ill., graph. Darst. |
| ISBN: | 1581134614 |
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| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV014622231 | ||
| 003 | DE-604 | ||
| 005 | 20030514 | ||
| 007 | t| | ||
| 008 | 020809s2002 xx ad|| |||| 10||| eng d | ||
| 020 | |a 1581134614 |9 1-58113-461-4 | ||
| 035 | |a (OCoLC)59465793 | ||
| 035 | |a (DE-599)BVBBV014622231 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-739 |a DE-91G |a DE-83 |a DE-29T | ||
| 084 | |a DAT 810f |2 stub | ||
| 084 | |a TEC 630f |2 stub | ||
| 111 | 2 | |a Design Automation Conference (Association for Computing Machinery) |n 39 |d 2002 |c New Orleans, La. |j Verfasser |0 (DE-588)10051749-3 |4 aut | |
| 245 | 1 | 0 | |a Proceedings 2002 |b Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 |c 39th Design Autmation Conference, DAC |
| 246 | 1 | 3 | |a DAC 2002 |
| 246 | 1 | 3 | |a Proceedings of the 39th Design Automation Conference |
| 264 | 1 | |a New York, NY |b ACM Press |c 2002 | |
| 300 | |a XXXVI, 919 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |2 gnd-content | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009938488&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009938488 | |
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| _version_ | 1820868164179722240 |
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| adam_text |
Table
of
Contents
General Chair's Welcome
.
і
Executive Committee
.
iii
Technical Program Committee
.
v
Panel Sub-Committee
.viii
Student Design Contest Judges
.viii
Exhibitor Liaison Committee
.ix
Opening Keynote Address
-
Hajime Sasaki
.
χ
Thursday Keynote Address
-
Jerry Fiddler
.xi
2002
Best Paper Award
.xii
Marie R.
Pistilli
Women in EDA Achievement Award
.xii
ACM/SIGDA Outstanding New Faculty Award
.xii
2002
IEEE CASS Fellows
.xiii
CAD Transactions Best Paper Award
.xiii
VLSI Transactions Best Paper Award
.xiii
Outstanding Young Author Award
.xiii
ACM/SIGDA Distinguished Service Award
.xiii
The P.O.
Pistilli
Scholarship for Advancement in Computer Science
.xiv
2001
DAC
P.O.
Pistilli
Undergraduate Scholarships
.xiv
Design Automation Conference Graduate Scholarships
.xiv
DAC
2002
Student Design Content Winners
.xv
Reviewers
.xvi
40th Design Automation Conference Call for Papers
.xxi
Session
1
PANEL: Wall Street Evaluates EDA
Chair:
Aart de Geus
Organizers: Sharon Turnoy, Deirdre Hanford
Panelists:
Moshe
Gavrielov, Richard Goering,
Lucio
Lanza, Vishal Saluja, Jay Vleeschhouwer
.
Session
2
Web and IP Based Design
Chair: Gang Qu
Organizers: Ahmed A. Jerraya,
Krzysztof
Kuchcinski
2.1
IP Delivery for FPGAs Using Applets and JHDL
Michael J. Wirthlin, Brian McMurtrey
.2
2.2
Watermarking Integer Linear Programming Solutions
Seapahn Megerian,
Milenko
Drinić,
Miodrag
Ρ
otkonjak
.8
23
Model Design Using Hierarchical Web-Based Libraries
Fabrice Bernardi,
Jean-François
Santuccì
.
^
2.4
Behavioral Synthesis via Engineering Change
Milenko
Drinić, Darko
Kirovski
.
18
Session 3
Design
Innovations
for Embedded Processors
Chair: Gang Qu
Organizers: Grant E. Martin, Majid Sarrafzadeh
3.1
A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation
Achim
Nohl,
Gunnar
Braun,
Oliver Schliebusch,
Rainer Leupers, Heinrich Meyr,
Andreas
Hofmann
.22
3.2
A Fast On-Chip Profiler Memory
Roman Lysecky, Susan Cotterell, Frank Vahid
.28
33
Design of an One-cycle Decompression Hardware for Performance Increase in Embedded Systems
Haris
Lekatsas, Jörg
Henkel, Venkata Jakkula
.34
Session
4
Passive Model Order Reduction
Chair: Jacob White
Organizers: Jaijeet Roychowdhury, Mustafa Celik
4.1
A Factorization-Based Framework for Passivity-Preserving Model Reduction of RLC Systems
Q.
Su,
V. Balakrishnan, C.-K. Koh
.40
4.2
Model Order Reduction for Strictly Passive and Causal Distributed Systems
Luca
Daniel, Joel R. Phillips
.46
43
Guaranteed Passive Balancing Transformations for Model Order Reduction
Joel R. Phillips,
Luca
Daniel, L. Miguel
Silveira
.52
Session
5
New Perspectives in Physical Design
Chair: Steven
Teig
Organizers: Ralph Otten, Timothy
Kam
5.1
Uncertainty-Aware Circuit Optimization
Xiaoliang
Bai,
Chandu Visweswariah, Philip
N.
Strenski, David J. Hathaway
.58
5.2
Congestion-Driven Codesign of Power and Signal Networks
Haihua
Su,
Jiang
Hu, Sachin
S.
Sapatnekar,
Sani
R. Nassif.
.64
53
On Metrics for Comparing Routability Estimation Methods for FPGAs
Parivallal
Kannan,
Shankar Balachandran, Dinesh Bhatia
.70
Session
6
PANEL: Tools or Users: Which is the Bigger Bottleneck?
Chair: Andrew B. Kahng
Organizer: Bob
Dahlberg
Panelists: Ron
Collett,
Patrick Groeneveld, Lambert Van
den Hoven,
Lavi Lev,
Nancy Nettleton, Paul Rodman
.76
Session
7
Special Session: Life after CMOS: Imminent or Irrelevant?
Chairs: Dennis Sylvester, Kaustav Banerjee
Organizers: Dennis Sylvester, Kaustav Banerjee
7.1
Life Is CMOS: Why Chase the Life After?
George
Sery,
Shekhar
Borkor,
VivekDe
.78
7.2
The Next Chip Challenge: Effective Methods for Viable Mixed Technology SoCs
H.
Bernhard Pogge.
84
73
Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
Adrian M. Ionescu, MichelJ. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques
Gautier
.88
7.4
Carbon Nanotube Field-Effect Transistors and Logic Circuits
R.
Martel,
V. Derycke, J. Appenzeller, S. Wind, and Ph. Avouris
.94
Session
8
Formal Verification
Chair: Yaron
Wolfsthal
Organizers: Carl Pixley,
Karem
Sakallah
8.1
Efficient State Representation for Symbolic Simulation
Valeria Bertacco, Kunle Olukotun
.99
8.2
Handling Special Constructs in Symbolic Simulation
Al/redKölbl,
James Kukula, Kurt Antreich, Robert
Damiano.105
83
A Hybrid Verification Approach: Getting Deep into the Design
Scott Hazelhurst, GilaKamhi,
Osnat Weissberg, LimorFix.
Ill
8.4
Can BDDs Compete with SAT Solvers on Bounded Model Checking?
Gianpiero Cabodi, Paolo Camurati,
Stefano Quer.117
Session
9
High Level Specification and Design
Chair: Andreas Kanstein
Organizers: Limor Fix, Shin-ichi
Minato
9.1 RTL
С
-Based Methodology for Designing and Verifying a Multi-Threaded Processor
Luc
Séméria,
Andrew Seawright,
Renu
Mehra, Daniel Ng, Arjuna Ekanayake, Barry Pangrle
.123
9.2
High-Level Specification and Automatic Generation of DP Interface Monitors
Marcio
T.
Oliveira,
Alan
J.
Ни
.129
93
Achieving Maximum Performance: A Method for the Verification of Interlocked
Pipeline Control Logic
Kerstin
Eder,
Geoff Barrett.
.135
9.4
Formal Verification of Module Interfaces against Real Time Specifications
Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee
.141
Session
10
Timing Abstraction
Chair: Mark
Hahn
Organizers: Chandu Visweswariah,
Narendra
V. Shenoy
10.1
Automated Timing Model Generation
AjayJ.
Daga, Loa
Mize,
Subramanyam Sripada, Chris Wolff, Qiuyang Wu
.146
10.2
Timing Model Extraction of Hierarchical Blocks by Graph Reduction
Cho W.Moon, Harish Kriplani, Krishna P. Belkhale
.152
103
Efficient Stimulus Independent Timing Abstraction Model Based on a New Concept
of Circuit Block Transparency
Martin Foltin, Brian Foutz, Sean Tyler
.¡58
10.4
An Implication-based Method to Detect Multi-Cycle Paths in Large Sequential Circuits
Hiroyuki Higuchi
.
¡64
Session 11
Special Session: E-Textiles
Chair
& Organizer: Majid
Sarrafżadeh
11.1
TO BE ANNOUNCED
11.2
The Wearable Motherboard: A Framework for Personalized Mobile Information Processing (PMIP)
Sugmee Park, Kenneth Mackenzie,
Sundaresan
Jayaraman
.170
113
Challenges and Opportunities in Electronic Textiles Modeling and Optimization
Diana Marculescu,
Radu
Marculescu, PradeepK. Khosla
.175
Session
12
PANEL: Analog Intellectual Property: Now? Or Never?
Chair: Stephen
Ohr
Organizers: Linda
Marchant,
Philippe Magarshack
Panelists: Masao Hotta, Mike Brunoli, Felicia James, Rudy Koch, Roy McGuffin, Andrew Moore
.181
Session
13
Low-Power System Design
Chair: Giovanni
De Micheli
Organizers:
Renu
Mehra, Enrico
Macii
13.1
Task Scheduling and Voltage Selection for Energy Minimization
Yumin Zhang, Xiaobo (Sharon)
Ни,
Danny
Z.
Chen
.183
13.2
Battery-Conscious Task Sequencing for Portable Devices Including Voltage/Clock Scaling
Daler
Rakhmatov,
Sarma
Vrudhula, Chaitali Chakrabarti
.189
133
An Energy Saving Strategy Based on Adaptive Loop Parallelization
/.
Kadayif, M. Kandemir, M. Karakoy.
.195
Session
14
Fabric-Driven Logic Synthesis
Chair:
Maciej Ciesielski
Organizers:
Małgorzata Merek-Sadowska,
Steven Nowick
14.1
River PLAs: A Regular Circuit Structure
Fan Mo, Robert K. Brayton
.201
14.2
WITHDRAWN
143
Layout-Aware Synthesis of Arithmetic Circuits
Junhyung Urn, Taewhan Kim
.207
Session
15
Memory Management and Address Optimization in Embedded Systems
Chair: Nikil Dutt
Organizers:
Diederik Verkest,
Luca
Benini
15.1
Automatic Data Migration for Reducing Energy Consumption in Multi-Bank Memory Systems
V.
De La Luz,
M.
Kandemir,
I. Kolcu
.213
15.2
Exploiting Shared Scratch Pad Memory Space in Embedded Multiprocessor Systems
M. Kandemir, J. Ramanujam, A. Choudhary
.219
153
Address Assignment Combined with Scheduling in DSP Code Generation
Yoonseo Choi, Taewhan Kim
.225
Session 16
Special Session:
Optics: Lighting the Way to EDA Riches?
Chair: Jaijeet Roychowdhury
Organizers: Jaijeet Roychowdhury, Joel R. Phillips
16.1
Multifunctional Photonic Integration for the Agile Optical Internet
Edward H. Sargent
.231
16.2
Computer Aided Design of Long-Haul Optical Transmission Systems
James G. Maloney, Brian E. Brewington, Curtis R.
Menyük
.235
163
A Fast Optical Propagation Technique for Modeling Micro-Optical Systems
Timothy P.
Kurzweg,
Steven P.
Levitán,
Jose A. Martinez, MarkKahrs, DonaldM. Chiarulli
.236
Session
17
PANEL: Nanometer Design: What Hurts Next.?
Chair: Lawrence T. Pileggi
Organizers: Rob A.
Rutenbar,
Andrew B. Kahng
Panelists: Bob Brodersen, Anthony Hill, John Kibarian,
Desmond A. Kirkpatrick, Mitsumasa Koyanagi, MarkLavin
.242
Session
18
Novel DFT, BIST and Diagnosis Techniques
Chair: Rathish Jayabharathi
Organizers: Kwang-Ting (Tim) Cheng, T. M.
Мак
18.1
Low-Cost Sequential ATPG with Clock-Control DFT
Miron Abramovici, Xiaoming Yu, Elizabeth
M
Rudnick
.243
18.2
Effective Diagnostics through Interval Unloads in a BIST Environment
Peter
Wohl,
John A. Waicukauski, Sanjay
Patel,
Greg Maston.249
18
J
On Output Response Compression in the Presence of unknown Output Values
Irith Pomeranz, Sandip Kundu, SudhakarM. Reddy
.
255
18.4
Software-Based Diagnosis for Processors
Li Chen, Sujit
Dey
.
Session
19
Case Studies in Embedded System Design
Chair: Wayne Wolf
Organizers: Anand Raghunathan, Xiaobo (Sharon) Hu
19.1
Design of a High-Throughput Low-Power IS95 Viterbi Decoder ^
XunLiu, Marios C. Papaeflhymiou
.
19.2
A Detailed Cost Model for Concurrent Use With Hardware/Software Co-Design
Daniel Ragan, Peter
Sandborn,
Paul StoaL·
.;.
193
Efficient Code Synthesis from Extended Dataflow Graphs for Multimedia Applications
HyunokOh, SoonhoiHa
.
Session
20
Theoretical Foundations of Embedded System Design
Chair: Rajesh Gupta
Organizers: Annette Reutter, Donatella Sciuto
20.1
Transformation Based Communication and Clock Domain Refinement for System Design
Ingo
Sander, Axel Jantsch
.
20.2
Model Composition for Scheduling Analysis in Platform Design
Kai Richter, Dirk Ziegenbein,
Marek
Jersak, Rolf Ernst.'."".'"".'-¿¿."n"".
203
Timed
Compiled-Code Simulation
of Embedded
Software
for
Performance
Analysis of
SOC
Design
Jong-YeolLee, In-Cheol
Park
."
xxvii
Session 21
Equivalence Verification
Chair: Ziyad
Hanna
Organizer: Shin-ichi
Minato
21.1
Automated Equivalence Checking of Switch Level Circuits
Simon Jolly,
Afanas Parashkevov,
TimMcDougall
.299
21.2
A Practical and Efficient Method for Compare-Point Matching
Demos Anastasakis, Robert
Damiano,
Hi-Keung Tony Ma, TedStanion
.305
21.3
Self-referential Verification of Gate-level Implementations of Arithmetic Circuits
Ting-Tsai Chang, Kwang-Tmg (Tim) Cheng
.311
Session
22
PANEL: Whither (or Wither?) ASIC Handoff
Chair: Michael Santarini
Organizers: Sudhakar Jilla, Mark Miller
Panelists: Tommy
Eng,
Sandeep Khanna, Kamalesh Ruparel, Tom Russell,
Kazu
Yantada.
317
Session
23
Embedded Software Automation: From Specification to Binary
Chair: Joerg
Henkel
Organizers: Marco
Di Natale,
Xiaobo (Sharon) Hu
23.1
Software Synthesis from Synchronous Specification Using Logic Simulation Techniques
Yunjian Jiang, Robert K. Brayton
.319
23.2
Complex Library Mapping for Embedded Software Using Symbolic Algebra
Armila Peymandoust,
Tajana Simunic, Giovanni
De Micheli.
325
233
Retargetable Binary Utilities
MaghsoudAbbaspour, Jianwen Zhu
.331
Session
24
Applications of Reconfigurable Computing
Chair:
Ivo Bolsens
Organizers: Grant E. Martin, Kurt Keutzer
24.1
Exploiting Operation Level Parallelism through Dynamically Reconfigurable Datapaths
ZhiningHuang, SharadMalik
.337
24.2
Dynamic Hardware
Plugins
in an FPGA with Partial Run-time Reconfiguration
Edson
L.
Horta,
John W.
Lockwood,
David E. Taylor, David Parlour
.343
243
A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read
Channel Simulator
Jinghuan Chen, Jaekyun Moon, Kia Bazargan
.349
Session
25
New Test Methods Targeting Non-Classical Faults
Chair: Rob Aitken
Organizers: Miron Abramovici, T. M.
Mak
25.1
Embedded Software-Based Self-Testing for SoC Design
A. Krstić,
W.-C. Lai, L. Chen, K.-T. Cheng,
S. Dey
.355
25.2
A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization
Swamp Bhunia, KaushikRoy, Jaume
Segura
.361
25
J
Signal
Integrity
Fault Analysis Using Reduced-Order Modeling
Amir Attarha, Mehrdad
Nomarti.
. 357
25.4
Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clock Schemes
Jing-JiaLiou,
Li
-С.
Wang, Kwang-Ting (Tim) Cheng, Jennifer
Dworak,
M.
Ray Mercer,
RohitKapur, Thomas W. Williams
.37]
Session
26
Special Session: How Do You Design a 10M Gate ASIC?
Chair: Ahmed A. Jerraya
Organizers: Ahmed A. Jerraya, Kurt Keutzer
26.1
Going Mobile: The Next Horizon for Multi-million Gate Designs in the Semi-Conductor Industry
Christian Berthet
.375
Session
27
Power Distribution Issues
Chair:
Sachin Sapatnekar
Organizers: Abhijit Dharchoudhury, Tadahiro Kuroda
27.1
HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for
RLKC Power Delivery
YahongCao, Yu-MinLee, Tsung-Hao Chen, Charlie Chung-Ping Chen
.379
27.2
High-Level Current Macro-Model For Power-Grid Analysis
Srinivas Bodapati, FaridN. Najm
.385
27
J
Macro-Modeling Concepts For The Chip Electrical Interface
Brian W.Amick, ClaudeR.
Gauthier, DeanLiu
.391
27.4
Modeling and Analysis of Regular Symmetrically
Structured Power/Ground Distribution Networks
Hui
Zheng, Lawrence T. Pileggi
.395
27. 5
Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise
Reduction Using Folding of Supply Current Transients
Mustafa Badaroglu, Kris
Tiri,
Stéphane
Donnay,
Piet
Wambacą,
Ingrid Verbauwhede,
Georges Gielen,
Hugo De Man.
Session
28
Advances in Synthesis
Chair:
Marek Perkowski
Organizers:
Soha
M. Hassoun, Yusuke Matsunaga
28.1
Resynthesis
and Peephole
Transformations
for the Optimization
of Large-Scale Asynchronous Systems
Tiberiu Chelcea, Steven M. Nowick
.405
28.2
Design of Asynchronous Circuits by Synchronous CAD Tools
Alex Kondratyev, Kelvin Lwin
.411
283
Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow
Christos
P. Sotiriou
.
415
28.4
Transformation Rules for Designing CNOT-based Quantum Circuits
Kazuolwama, Yahiko Kambayashi, Shigent Yamashita
.419
28.5
Fast Three-Level Logic Minimization Based on Autosymmetry
Anna Bernasconi,
Valentina
Ciriani,
Fabrizio
Luccio,
Linda
Pagii
.425
xxix
Session 29
Analog
Synthesis
& Design
Methodology
Chair: C.-J. Richard Shi
Organizers: Joel R. Phillips, Kartikeya Mayaram
29.1
An Efficient Optimization-based Technique to Generate Posynomial
Performance Models for Analog Integrated Circuits
Walter Daems, George Gielen, Willy
Sansen
.431
29.2
Remembrance of Circuits Past: Macromodeling by Data Mining in Large Analog Design Spaces
HongzhouLiu, AmitSinghee, Rob A.
Rutenbar, L. Richard Carley.437
293
Optimal Design of
Delta-Sigma
ADCs by Design Space Exploration
Ovidiu Bajdechi, Georges Gielen,
Johan
H. Huijsing
.443
19
A Systematic Design of a
200
MS/s 8-bit Interpolating/ Averaging A/D Converter
J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert, Georges Gielen
.449
Session
30
Low-Power Physical Design
Chair: Massoud Pedram
Organizers: Chaitali Chakrabarti,
Sarma
Vradhula
30.1
Petri
Net Modeling of Gate and Interconnect Delays for Power Estimation
AshokK. Murugavel,
N.
Ranganathan
.455
30.2
Power Estimation in Global Interconnects and its Reduction Using
a Novel Repeater Optimization Methodology
Pawan Kapur, Gaurav Chandra, Krishna
C. Saraswat
.461
303
Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltage
Seong-Ook Jung, Ki-Wook Kim, Sung-MoKang.
.467
30.4
DRG-Cache: A Data Retention Gated-Ground Cache for Low Power
Amit
Agarwal,
Hai Li,
KaushikRoy.
.473
Session
31
PANEL: Unified Tools for SoC Embedded Systems:
Mission Critical, Mission Impossible or Mission Irrelevant?
Chair: Gary Smith
Organizers: Daya Nadamuni, Sharad Malik
Panelists: Rick Chapman, John Fogelin, KurtKeutzer, Grant Martin, BrianBailey
.479
Session
32
Multi-Voltage, Multi-Threshold Design
Chair: Rajendran Panda
Organizers:
Renu
Mehra,
Sarma
Vrudhula
32.1
Dynamic and Leakage Power Reduction in MTCMOS
Circuits Using an Automated Efficient Gate Clustering Technique
Mohab
Anis,
Shawki Areibi,
Mohamed
Mahmoud, Mohamed
Elmasry
.480
32.2
Total Power Optimization By Simultaneous Dual-Vt Allocation and Device Sizing
in High Performance Microprocessors
Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven Burns, Venkatesh Govindarajulu,
VtvekDe, Shekhar Borkar
.486
323
An Optimal Voltage Synthesis Technique for a Power-Efficient Satellite Application
Dong-InKang, JinwooSuh, Stephen P. Crago
.492
Session 33
Advanced Simulation
Techniques
Chair: L.
Miguel
Silveira
Organizers: Georges Gielen, Kartikeya Mayaram
33.1 Fast
and Accurate
Behavioral
Simulation
of Fractional-N
Frequency
Synthesizers
and other
PLL/DLL
Circuits
Michael
H.
Perrott.498
33.2
Time-domain Steady-state Simulation of Frequency-Dependent
Components Using Multi-interval Chebyshev Method
Baolin Yang, Joel R. Phillips
.504
333
A Time-domain RF Steady-State Method for Closely Spaced Tones
Jaijeet Roychowdhury
.510
33.4
An Algorithm for Frequency-Domain Noise Analysis in Nonlinear Systems
Giorgio
Cosinovi
.514
Session
34
Design Methodologies Meet Network Applications
Chair: Anand Raghunathan
Organizers: Anand Raghunathan, Marco
Di Natale
34.1
System-level Performance Optimization of the Data Queueing
Memory Management in High-Speed Network Processors
Ch. Ykman-Couvreur, J. Lambrecht, D. Verkest, F. Catthoor, A. Nikologiannis, G. Konstantoulakis
.518
34.2
Analysis of Power Consumption on Switch Fabrics in Network Routers
Terry
Jao
Ye,
Luca
Benini,
Giovanni
De Micheli
.524
343
Memory Optimization in Single Chip Network Switch Fabrics
David Wheliham, Herman Schmit
.530
Session
35
Advances in Analog Modeling
Chair: Alan Mantooth
Organizers: Joel R. Phillips, Kartikeya Mayaram
35.1
Behavioral Modeling of (Coupled) Harmonic Oscillators
Piet
Vanassche, Georges Gielen, Willy
Sansen
.536
35.2
Model Checking Algorithms for Analog Verification
Walter Hartong, Lars Hedrich, Erich
Barke.542
353
Regularization of Hierarchical VHDL-AMS Models using Bipartite Graphs
Jochen
Mades,
Manfred Glesner
.548
35.4
Improving the Generality of the Fictitious Magnetic Charge Approach
to Computing Inductances in the Presence of Permeable Materials
Yehia Massoud, Jacob White
.552
Session
36
Advances in Timing and Simulation
Chair: David J. Hathaway
Organizers: Louis Scheffer,
Narendra
V. Shenoy
36.1
A General Probabilistic Framework for Worst Case Timing Analysis
Michael Orshansky, Kurt Keutzer
.556
36.2
False Timing Path Identification Using ATPG Techniques and Delay-Based Information
JingZeng,
Magdy
Abadir, Jacob Abraham
.562
xxxi
36.3
False-Path-Aware Statistical Timing Analysis and Efficient Path
Selection for Delay Testing and Timing Validation
Jing-JiaLiou, Angela
Krstić,
Li-C.
Wang, Kwang-Ting (Tim) Cheng
.566
36.4
A Fast, Inexpensive and Scalable Hardware Acceleration Technique for Functional Simulation
Srihari Cadambi, Chandra S. Mulpuri, PranavN. Ashar
.570
Session
37
PANEL: Formal Verification Methods: Getting around the Brick Wall
Chair: David Dill
Organizers: Nate James, Shishpal Rawat
Panelists:
Gérard
Berry, LimorFix, Harry Foster, Rajeev Ranjan,
Gunnar
Stalmarck, Curt Widdoes.
576
Session
38
Routing and Buffering
Chair: Noel
Menezes
Organizers: Charles J. Alpert, Steven
Teig
38.1
S-Tree: A Technique for Buffered Routing Tree Synthesis
Milos
Hrkic, John Lillis
.578
38.2
An Algorithm for Integrated Pin Assignment and Buffer Planning
HuaXiang, Xiaoping Tang, D. F. Wong
.584
383
An Efficient Routing Database
Narendra
V.Shenoy,
William Nicholls
.590
Session
39
System on Chip Design
Chair: Rolf Ernst
Organizers:
Krzysztof
Kuchcinski, Miodrag Potkonjak
39.1
Automatic Generation of Embedded Memory Wrapper for Multiprocessor SoC
Ferid
Gharsalli, SamyMefiali,
Frédéric
Rousseau, Ahmed A. Jerraya
.596
39.2
A Novel Synthesis Technique for Communication Controller Hardware from Declarative Data
Communication Protocol Specifications
Robert
Siegmund, Dietmar
Muller.
602
39
J
An Integrated Algorithm for Memory Allocation and Assignment in High-level Synthesis
JaewonSeo, TaewhanKim, PreetiR. Panda
.608
39.4
High-Level Synthesis of Multiple-Precision Circuits Independent of Data-Objects Length
M. C. Molina, J.
M. Mendias,
R.
Hermida
.612
Session
40
Timing Analysis and Memory Optimization for Embedded Systems
Chair: Giuseppe Lipari
Organizers: Marco
Di Natale,
Xiaobo (Sharon) Hu
40.1
Schedulability of Event-Driven Code Blocks in
Real-Time
Embedded Systems
Samarjit Chakraborty, Thomas Erlebach, Simon
Künzli, Lothar Thiele.616
40.2
Associative Caches in Formal Software Timing Analysis
Fabian Wolf, Jan Staschulat, Rolf Ernst
.622
40.3
Compiler-Directed Scratch Pad Memory Hierarchy Design and Management
M. Kandemir, A. Choudhary
.628
Session 41
Processors
and Accelerators for Embedded Applications
Chair: Chris Rowen
Organizers: Kurt Keutzer, Majid Sarrafzadeh
41.1
Unlocking the Design Secrets of a
2.29
Gb/s Rijndael Processor
Patrick R. Schaumont, Henry Kuo,
Ingrid
M. Verbauwhede
.634
41.2
The iCORE™
520
MHz Synthesizable CPU Core
Nick Richardson,
Lun
Bin Huang, Razak Hossain, Tommy Zounes, Naresh
Soni,
Julian Lewis
.640
413
A Flexible Accelerator for Layer
7
Networking Application
Gökhan
Memik,
William H Mangione-Smith
.646
Session
42
PANEL: What's the Next EDA Driver?
Chair: Jan Rabaey
Organizers: Joachim
Kunkel,
Dennis Brophy
Panelists: Raul Camposano, Davoud
Šamani,
Larry
Lerner, Rick
Hetherington
.652
Session
43
Cross-Talk Noise Analysis and Management
Chair: Cheng-KokKoh
Organizers: Kaushik Roy, Noel
Menezes
43.1
Estimation of the Likelihood of
Capacitive
Coupling Noise
Sarma
B. K. Vrudhula, David Blaauw,
Suparnas
Sirichotiyakul
.653
43.2
Crosstalk Noise Estimation for Noise Management
Paul B. Morton, Wayne Dai
.659
43
J
Variable Frequency Crosstalk Noise Analysis: A Methodology to Guarantee Funtionality
from dc to
f,,,»!
Byron
Krauter,
David Widiger
.665
43.4
Towards Global Routing With RLC Crosstalk Constraints
James D.Z. Ma, Lei He
.669
Session
44
Test Cost Reduction for SOCS
Chair: Yervant Zorian
Organizers: Seiji Kajihara, Kwang-Ting (Tim) Cheng
44.1
Reduction of
SOC
Test Data Volume, Scan Power and Testing Time
Using Alternating Run-length Codes
Anshuman Chandra, Krishnendu Chakrabarty
.673
44.2
Embedded Test Control Schemes for Compression in SOCs
Douglas Kay, Sung Chung, Samiha Mourad.
.679
443
Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling,
and Tester Data Volume Reduction for SOCs
Икгат
Iyengar, Krishnendu Chakrabarty, Erik Jan
Marinissen
.685
Session
45
Scheduling Techniques for Embedded Systems
Chair: Rolf Ernst
Organizers:
Diederik Verkest,
Donatella Sciuto
45.1
Communication Architecture Based Power Management for Battery Efficient System Design
Kanishka Lahiri, Anand Raghunathan, SujitDey
.691
45.2
Scheduler-Based DRAM Energy Management
V.Delaluz, A. Sivasubramaniam, M. Kandemir,
N.
Vijaykrishnan, M. J.
Irwin.697
453
An Integer Linear Programming Based Approach for Parallelizing Application in On-Chip
Multiprocessors
I. Kadayif, M. Kandemir, U. Sezer
.703
Session
46
Special Session: Designing SoCs for Yield Improvement
Chair: Srivaths Ravi
Organizers: Anand Raghunathan, Alfred E. Dunlop
46.1
Embedding Infrastructure IP for
SOC
Yield Improvement
Yervant Zorian
.709
46.2
Using Embedded FPGAs for SoC Yield Improvement
Miron Abramovici, Charles Stroud, Marty
Emmert
.713
Session
47
Advances in SAT
Chair: Joao
Marques-Silva
Organizers:
Małgorzata
Merek-Sadowska,
Soha
M. Hassoun
47.1
A Proof Engine Approach to Solving Combinational Design Automation Problems
Gunnar
Andersson,
PerBjesse, Byron Cook, Ziyad
Hanna
.725
47.2
Solving Difficult SAT Instances in the Presence of Symmetry
FadiA. Aloul, Arathi
Romani,
Igor
Ĺ.
Markov,
Karem
A. Sakallah
.731
473
Satometer:
How Much Have We Searched?
FadiA. Aloul, Brian D. Sierawski,
Karem
A. Sakallah
.737
47.4
SAT with Partial Clauses and Back-Leaps
Sławomir
Pilarski,
Gracia
Ни.
743
47.5
Combining Strengths of Circuit-based and CNF-based
Algorithms for a High-Performance SAT Solver
Malay
К
Ganai, Lintao Zhang, Pranav Ashar, Aarti Gupta, SharadMalik
. 747
Session
48
Inductance and Substrate Analysis
Chair: Noel
Menezes
Organizers: Jaijeet Roychowdhury, Mustafa Celik
48.1
A Solenoidal Basis Method For Efficient Inductance Extraction
Hemant Mahawar, Vivek
Sarin,
Weiping
Shi
.751
48.2
On the Efficacy of Simplified 2D On-Chip Inductance Models
TaoLin, Michael W. Beattie, Lawrence T. Pileggi.
.757
48
J
A Physical Model for the Transient Response of Capacitively
Loaded Distributed RLC Interconnects
Raguraman Venkatesan, Jeffrey A. Davis, James D. Me
indi
.765
48.4
HSpeedEx: A High-Speed Extractor for Substrate Noise
Analysis in Complex Mixed-Signal SOC
AdilKoukab, Catherine Dehollain, Michel Declercq
.767
48.5
Combined BEM/FEM Substrate Resistance Modeling
E. Schrik,
N.
P. van derMeijs
.771
Session 49
Development
of Processors and Communication Networks for Embedded Systems
Chair: Jan Rabaey
Organizers: Grant E. Martin, Majid Sarrafzadeh
49.1
System Design Methodologies for a Wireless Security Processing Platform
Srivaths Ravi, AnandRaghunathan, Nachiketh Potlapally, Murugan Sankaradass
.777
49.2
Constraint-Driven Communication Synthesis
Alessandro
Pinto,
Luca
P. Carloni, Alberto L. Sangiovanni-Vincentelli
.783
49.3
Component-Based Design Approach for Multicore SoCs
W.
Cesano,
A. Baghdadi,
L. Gauthier,
D.
Lyonnard,
G. Nicolescu, Y. Paviot,
S.
Yoo,
Α. Α.
Jerraya,
Μ.
Diaz-Nava.789
49 .4
Traffic Analysis for On-Chip Networks Design of Multimedia Applications
Girish
Varatkar,
Radu
Marculescu
.795
Session
50
Moving Towards More Effective Validation
Chair:
Magdy
Abadir
Organizers: Carl Pixley, Masahiro Fujita
50.1
Deriving a Simulation Input Generator and a Coverage Metric From a Formal Specification
Kanna
Shimizu, David L. Dill
.801
50.2
Hole Analysis for Functional Coverage Data
OdedLachish, Eitan Marcus, Shmuel Ur,
Avi
Ziv
.807
50.3
Effective Safety Property Checking Using Simulation-Based Sequential ATPG
ShouSheng, Koichiro Takayama,
Michaels.
Hsiao
.813
50.4
A Comparison of Three Verification Techniques:
Directed Testing, Pseudo-Random Testing and Property Checking
Mike G. Bartley, Darren Galpin, Tim Blackmore
.819
Session
51
Special Session: Energy Efficient Mobile Computing
Chair: Enrico
Macii
Organizer:
Mani Srivastava
51.1
Energy-Efficient Communication Protocols
Carla
F. Chiasserini, Pavan Nuggehalli, Vikram Srinivasan, RameshR. Rao
.824
51.2
Reliable and Energy-Efficient Digital Signal Processing
Naresh Shanbhag.
.830
513
CMOS: A Paradigm for Low Power Wireless?
Michiel Steyaert, Peter Vancorenland
.836
Session
52
Floorplanning and Placement
Chair: Ralph Otten
Organizers: Ralph Otten, Steven
Teig
52.1
TCG-S: Orthogonal Coupling of P*-admissible Representation for General Floorplans
Jai-MingLin, Yao-Wen Chang
.842
52.2
Floorplanning with Alignment and Performance Constraints
Xiaoping Tang, D.
F
Wong
.848
523
Algorithms for Simultaneous Satisfaction of Multiple Constraints and Objective Optimization
in a Placement Flow with Application to Congestion Control
KeZhong, ShantanuDutt
.854
Session 53
Circuit
Effects in Static Timing
Chair: Jamil
Kawa
Organizers: Chandu Visweswariah, Louis Scheffer
53.1
Coping with Buffer Delay Change Due to Power and Ground Noise
Lauren
Hui
Chen,
Małgorzata
Marek-Sadowska, Forrest Brewer
.860
53.2
Osculating Thevenin Model for Predicting Delay and Slew of Capacitively Characterized Cells
Bernard
N.
Sheehan
.866
53
J
Timed Pattern Generation for Noise-on-Delay Calculation
Seung
Hoon
Choi,
Florentin
Dartu, Kaushik Roy
.870
53.4
VeriCDF: A New Verification Methodology for Charged Device Failures
JaesikLee, Ki-WookKim, Sung-MoKang
.874
Session
54
Design Space Exploration for Embedded Systems
Chair:
Henk
Corporaal
Organizers: Jo Dale Carothers,
Luca
Benini
54.1
A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures
Lothar Thiele,
Samarjit Chakraborty, Matthias Gries, Simon
Künzli.880
54.2
Energy Estimation and Optimization of Embedded VLIW Processors based
on Instruction Clustering
A. Bona,
M. Sami, D. Scmto, C.
Silvano,
V.
Zaccaria, R. Zafalon
.886
543
Energy
Exploration
and Reduction of
SDRAM Memory Systems
Yongsoo Joo, Yongseok Choi,
Hojun
Shim,
Hyung Gyu Lee,
Kwanho Kim,
Naehyuck
Chang
.892
Session
55
Behavioral Synthesis
Chair:
Petru
Eles
Organizers: Ahmed A. Jerraya,
Krzysztof Kuchcinski
55.1
Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks
Sumit Gupta,
ЋтоПуКат,
Michael Kishinevsky, Shai
Rotem,
NickSavoiu, NikilDutt, Rajesh Gupta, AlexNicolau
.898
55.2
Forward-Looking Objective Functions: Concept
&
Applications in High Level Synthesis
Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak
.904
55
J ILP-Based
Engineering Change
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng, Miodrag Potkonjak
.910
Author Index |
| any_adam_object | 1 |
| author_corporate | Design Automation Conference (Association for Computing Machinery) New Orleans, La |
| author_corporate_role | aut |
| author_facet | Design Automation Conference (Association for Computing Machinery) New Orleans, La |
| author_sort | Design Automation Conference (Association for Computing Machinery) New Orleans, La |
| building | Verbundindex |
| bvnumber | BV014622231 |
| classification_rvk | SS 2002 |
| classification_tum | DAT 810f TEC 630f |
| ctrlnum | (OCoLC)59465793 (DE-599)BVBBV014622231 |
| discipline | Technik Informatik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 c 4500</leader><controlfield tag="001">BV014622231</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20030514</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">020809s2002 xx ad|| |||| 10||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1581134614</subfield><subfield code="9">1-58113-461-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)59465793</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV014622231</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-739</subfield><subfield code="a">DE-91G</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 810f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">TEC 630f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">Design Automation Conference (Association for Computing Machinery)</subfield><subfield code="n">39</subfield><subfield code="d">2002</subfield><subfield code="c">New Orleans, La.</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)10051749-3</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Proceedings 2002</subfield><subfield code="b">Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002</subfield><subfield code="c">39th Design Autmation Conference, DAC</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">DAC 2002</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Proceedings of the 39th Design Automation Conference</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York, NY</subfield><subfield code="b">ACM Press</subfield><subfield code="c">2002</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXXVI, 919 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009938488&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-009938488</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift gnd-content |
| genre_facet | Konferenzschrift |
| id | DE-604.BV014622231 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:20:00Z |
| institution | BVB |
| institution_GND | (DE-588)10051749-3 |
| isbn | 1581134614 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009938488 |
| oclc_num | 59465793 |
| open_access_boolean | |
| owner | DE-739 DE-91G DE-BY-TUM DE-83 DE-29T |
| owner_facet | DE-739 DE-91G DE-BY-TUM DE-83 DE-29T |
| physical | XXXVI, 919 S. Ill., graph. Darst. |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | ACM Press |
| record_format | marc |
| spelling | Design Automation Conference (Association for Computing Machinery) 39 2002 New Orleans, La. Verfasser (DE-588)10051749-3 aut Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 39th Design Autmation Conference, DAC DAC 2002 Proceedings of the 39th Design Automation Conference New York, NY ACM Press 2002 XXXVI, 919 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009938488&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 |
| subject_GND | (DE-588)1071861417 |
| title | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 |
| title_alt | DAC 2002 Proceedings of the 39th Design Automation Conference |
| title_auth | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 |
| title_exact_search | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 |
| title_full | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 39th Design Autmation Conference, DAC |
| title_fullStr | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 39th Design Autmation Conference, DAC |
| title_full_unstemmed | Proceedings 2002 Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 39th Design Autmation Conference, DAC |
| title_short | Proceedings 2002 |
| title_sort | proceedings 2002 ernest n memorial convention center new orleans la june 10 14 2002 |
| title_sub | Ernest N. Memorial Convention Center, New Orleans, LA, June 10 - 14, 2002 |
| topic_facet | Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009938488&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT designautomationconferenceassociationforcomputingmachineryneworleansla proceedings2002ernestnmemorialconventioncenterneworleanslajune10142002 AT designautomationconferenceassociationforcomputingmachineryneworleansla dac2002 AT designautomationconferenceassociationforcomputingmachineryneworleansla proceedingsofthe39thdesignautomationconference |