Broadband packet switching technologies: a practical guide to ATM switches and IP routers
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
Wiley
2001
|
| Schriftenreihe: | A Wiley-Interscience publication
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XVI, 459 S. graph. Darst. |
| ISBN: | 0471004545 |
Internformat
MARC
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| 100 | 1 | |a Chao, H. Jonathan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Broadband packet switching technologies |b a practical guide to ATM switches and IP routers |c H. Jonathan Chao ; Cheuk H. Lam ; Eiji Oki |
| 264 | 1 | |a New York [u.a.] |b Wiley |c 2001 | |
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Datensatz im Suchindex
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| adam_text | BROADBAND PACKET SWITCHING TECHNOLOGIES A PRACTICAL GUIDE TO ATM
SWITCHES AND IP ROUTERS H. JONATHAN CHAO CHEUK H. LAM EMI OKI A
WILEY-LNTERSCIENCE PUBLICATION JOHN WILEY & SONS, INC. NEW YORK /
CHICHESTER / WEINHEIM / BRISBANE / SINGAPORE / TORONTO CONTENTS PREFACE
XIII 1 INTRODUCTION 1 1.1 ATM SWITCH SYSTEMS / 3 1.1.1 BASICS OF ATM
NETWORKS / 3 1.1.2 ATM SWITCH STRUCTURE / 5 1.2 IP ROUTER SYSTEMS / 8
1.2.1 FUNCTIONS OF IP ROUTERS / 8 1.2.2 ARCHITECTURES OF IP ROUTERS / 9
1.3 DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS / 13 REFERENCES / 14 2
BASICS OF PACKET SWITCHING 15 2.1 SWITCHING CONCEPTS / 17 2.1.1 INTERNAL
LINK BLOCKING / 17 2.1.2 OUTPUT PORT CONTENTION / 18 2.1.3 HEAD-OF-LINE
BLOCKING / 19 2.1.4 MULTICASTING / 19 2.1.5 CALL SPLITTING / 20 2.2
SWITCH ARCHITECTURE CLASSIFICATION / 21 2.2.1 TIME DIVISION SWITCHING /
22 VI CONTENTS 2.2.2 SPACE DIVISION SWITCHING / 24 2.2.3 BUFFERING
STRATEGIES / 34 2.3 PERFORMANCE OF BASIC SWITCHES / 37 2.3.1
INPUT-BUFFERED SWITCHES / 37 2.3.2 OUTPUT-BUFFERED SWITCHES / 40 2.3.3
COMPLETELY SHARED-BUFFER SWITCHES / 44 REFERENCES / 46 3 INPUT-BUFFERED
SWITCHES 49 3.1 A SIMPLE SWITCH MODEL / 50 3.1.1 HEAD-OF-LINE BLOCKING
PHENOMENON / 51 3.1.2 TRAFFIC MODELS AND RELATED THROUGHPUT RESULTS / 52
3.2 METHODS FOR IMPROVING PERFORMANCE / 53 3.2.1 INCREASING INTERNAL
CAPACITY / 53 3.2.2 INCREASING SCHEDULING EFFICIENCY / 54 3.3 SCHEDULING
ALGORITHMS / 57 3.3.1 PARALLEL ITERATIVE MATCHING (PIM) / 58 3.3.2
ITERATIVE ROUND-ROBIN MATCHING (/RRM) / 60 3.3.3 ITERATIVE ROUND-ROBIN
WITH SLIP (/SLIP) / 60 3.3.4 DUAL ROUND-ROBIN MATCHING (DRRM) / 62 3.3.5
ROUND-ROBIN GREEDY SCHEDULING / 65 3.3.6 DESIGN OF ROUND-ROBIN
ARBITERS/SELECTORS / 67 3.4 OUTPUT-QUEUING EMULATION / 72 3.4.1
MOST-URGENT-CELL-FIRST-ALGORITHM (MUCFA) / 72 3.4.2 CHUANG ET AL. S
RESULTS / 73 3.5 LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST ALGORITHM (LOOFA) /
78 REFERENCES / 80 4 SHARED-MEMORY SWITCHES 83 4.1 LINKED-LIST APPROACH
/ 84 4.2 CONTENT-ADDRESSABLE MEMORY APPROACH / 91 4.3 SPACE-TIME-SPACE
APPROACH / 93 4.4 MULTISTAGE SHARED-MEMORY SWITCHES / 94 4.4.1
WASHINGTON UNIVERSITY GIGABIT SWITCH / 95 4.4.2 CONCENTRATOR-BASED
GROWABLE SWITCH ARCHITECTURE / 96 4.5 MULTICAST SHARED-MEMORY SWITCHES /
97 CONTENTS VM 4.5.1 SHARED-MEMORY SWITCH WITH A MULTICAST LOGICAL QUEUE
/ 97 4.5.2 SHARED-MEMORY SWITCH WITH CELL COPY / 98 4.5.3 SHARED-MEMORY
SWITCH WITH ADDRESS COPY / 99 REFERENCES / 101 5 BANYAN-BASED SWITCHES
103 5.1 BANYAN NETWORKS / 103 5.2 BATCHER-SORTING NETWORK / 106 5.3
OUTPUT CONTENTION RESOLUTION ALGORITHMS / 110 5.3.1 THREE-PHASE
IMPLEMENTATION / 110 5.3.2 RING RESERVATION / 110 5.4 THE SUNSHINE
SWITCH / 112 5.5 DEFLECTION ROUTING / 114 5.5.1 TANDEM BANYAN SWITCH /
114 5.5.2 SHUFFLE-EXCHANGE NETWORK WITH DEFLECTION ROUTING / 117 5.5.3
DUAL SHUFFLE-EXCHANGE NETWORK WITH ERROR-CORRECTING ROUTING / 118 5.6
MULTICAST COPY NETWORKS / 125 5.6.1 BROADCAST BANYAN NETWORK / 127 5.6.2
ENCODING PROCESS / 129 5.6.3 CONCENTRATION / 132 5.6.4 DECODING PROCESS
/ 133 5.6.5 OVERFLOW AND CALL SPLITTING / 133 5.6.6 OVERFLOW AND INPUT
FAIRNESS / 134 REFERENCES / 138 6 KNOCKOUT-BASED SWITCHES 141 6.1
SINGLE-STAGE KNOCKOUT SWITCH / 142 6.1.1 BASIC ARCHITECTURE / 142 6.1.2
KNOCKOUT CONCENTRATION PRINCIPLE / 144 6.1.3 CONSTRUCTION OF THE
CONCENTRATOR / 146 6.2 CHANNEL GROUPING PRINCIPLE / 150 6.2.1 MAXIMUM
THROUGHPUT / 150 6.2.2 GENERALIZED KNOCKOUT PRINCIPLE / 152 6.3 A
TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH / 154 6.3.1 TWO-STAGE
CONFIGURATION / 154 VIII CONTENTS 6.3.2 MULTICAST GROUPING NETWORK / 157
6.3.3 TRANSLATION TABLES / 160 6.3.4 MULTICAST KNOCKOUT PRINCIPLE / 163
6.4 A FAULT-TOLERANT MULTICAST OUTPUT-BUFFERED ATM SWITCH / 169 6.4.1
FAULT MODEL OF SWITCH ELEMENT / 169 6.4.2 FAULT DETECTION / 172 6.4.3
FAULT LOCATION AND RECONFIGURATION / 174 6.4.4 PERFORMANCE ANALYSIS OF
RECONFIGURED SWITCH MODULE / 181 6.5 APPENDIX / 185 REFERENCES / 187 7
THE ABACUS SWITCH 189 7.1 BASIC ARCHITECTURE / 190 7.2 MULTICAST
CONTENTION RESOLUTION ALGORITHM / 193 7.3 IMPLEMENTATION OF INPUT PORT
CONTROLLER / 197 7.4 PERFORMANCE / 198 7.4.1 MAXIMUM THROUGHPUT / 199
7.4.2 AVERAGE DELAY / 203 7.4.3 CELL LOSS PROBABILITY / 206 7.5 ATM
ROUTING AND CONCENTRATION CHIP / 208 7.6 ENHANCED ABACUS SWITCH / 211
7.6.1 MEMORYLESS MULTISTAGE CONCENTRATION NETWORK / 212 7.6.2 BUFFERED
MULTISTAGE CONCENTRATION NETWORK / 214 7.6.3 RESEQUENCING CELLS / 217
7.6.4 COMPLEXITY COMPARISON / 219 7.7 ABACUS SWITCH FOR PACKET SWITCHING
/ 220 7.7.1 PACKET INTERLEAVING / 220 7.7.2 CELL INTERLEAVING / 222
REFERENCES / 224 8 CROSSPOINT-BUFFERED SWITCHES 227 8.1 OVERVIEW OF
CROSSPOINT-BUFFERED SWITCHES / 228 8.2 SCALABLE DISTRIBUTED ARBITRATION
SWITCH / 229 8.2.1 SDA STRUCTURE / 229 8.2.2 PERFORMANCE OF SDA SWITCH /
231 8.3 MULTIPLE-QOS SDA SWITCH / 234 8.3.1 MSDA STRUCTURE / 234
CONTENTS IX 8.3.2 PERFORMANCE OF MSDA SWITCH / 236 REFERENCES / 238 9
THE TANDEM-CROSSPOINT SWITCH 239 9.1 OVERVIEW OF INPUT-OUTPUT-BUFFERED
SWITCHES / 239 9.2 TDXP STRUCTURE / 241 9.2.1 BASIC ARCHITECTURE / 241
9.2.2 UNICASTING OPERATION / 242 9.2.3 MULTICASTING OPERATION / 246 9.3
PERFORMANCE OF TDXP SWITCH / 246 REFERENCES / 252 10 CLOS-NETWORK
SWITCHES 253 10.1 ROUTING PROPERTIES AND SCHEDULING METHODS / 255 10.2 A
SUBOPTIMAL STRAIGHT MATCHING METHOD FOR DYNAMIC ROUTING / 258 10.3 THE
ATLANTA SWITCH / 259 10.3.1 BASIC ARCHITECTURE / 261 10.3.2 DISTRIBUTED
AND RANDOM ARBITRATION / 261 10.3.3 MULTICASTING / 262 10.4 THE
CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH / 263 10.4.1 BASIC
ARCHITECTURE / 264 10.4.2 CONCURRENT ROUND-ROBIN DISPATCHING (CRRD)
SCHEME / 265 10.4.3 DESYNCHRONIZATION EFFECT OF CRRD / 267 10.5 THE PATH
SWITCH / 268 10.5.1 HOMOGENEOUS CAPACITY AND ROUTE ASSIGNMENT / 272
10.5.2 HETEROGENEOUS CAPACITY ASSIGNMENT / 274 REFERENCES / 277 11
OPTICAL PACKET SWITCHES 279 11.1 ALL-OPTICAL PACKET SWITCHES / 281
11.1.1 THE STAGGERING SWITCH / 281 11.1.2 ATMOS / 282 11.1.3 DUAN S
SWITCH / 283 11.2 OPTOELECTRONIC PACKET SWITCHES / 284 11.2.1 HYPASS /
284 11.2.2 STAR-TRACK / 286 X CONTENTS 11.2.3 CISNEROS AND BRACKETT S
ARCHITECTURE / 287 11.2.4 BNR SWITCH / 289 11.2.5 WAVE-MUX SWITCH / 290
11.3 THE 3M SWITCH / 291 11.3.1 BASIC ARCHITECTURE / 291 11.3.2 CELL
DELINEATION UNIT / 294 11.3.3 VCI-OVERWRITE UNIT / 296 11.3.4 CELL
SYNCHRONIZATION UNIT / 297 11.4 OPTICAL INTERCONNECTION NETWORK FOR
TERABIT IP ROUTERS / 301 11.4.1 INTRODUCTION / 301 11.4.2 A TERABIT IP
ROUTER ARCHITECTURE / 303 11.4.3 ROUTER MODULE AND ROUTE CONTROLLER /
306 11.4.4 OPTICAL INTERCONNECTION NETWORK / 309 11.4.5 PING-PONG
ARBITRATION UNIT / 315 11.4.6 OIN COMPLEXITY / 324 11.4.7 POWER BUDGET
ANALYSIS / 326 11.4.8 CROSSTALK ANALYSIS / 328 REFERENCES / 331 12
WIRELESS ATM SWITCHES 337 12.1 WIRELESS ATM STRUCTURE OVERVIEWS / 338
12.1.1 SYSTEM CONSIDERATIONS / 338 12.1.2 WIRELESS ATM PROTOCOL / 349
12.2 WIRELESS ATM SYSTEMS / 341 12.2.1 NEC S WATMNET PROTOTYPE SYSTEM /
341 12.2.2 OLIVETTI S RADIO ATM LAN / 342 12.2.3 VIRTUAL CONNECTION TREE
/ 342 12.2.4 BAHAMA WIRELESS ATM LAN / 343 12.2.5 NTT S WIRELESS ATM
ACCESS / 343 12.2.6 OTHER EUROPEAN PROJECTS / 243 12.3 RADIO ACCESS
LAYERS / 344 12.3.1 RADIO PHYSICAL LAYER / 344 12.3.2 MEDIUM ACCESS
CONTROL LAYER / 346 12.3.3 DATA LINK CONTROL LAYER / 346 12.4 HANDOFF
IN WIRELESS ATM / 347 12.4.1 CONNECTION REROUTING / 348 12.4.2 BUFFERING
/ 340 CONTENTS XI 12.4.3 CELL ROUTING IN A COS / 351 12.5
MOBILITY-SUPPORT ATM SWITCH / 352 12.5.1 DESIGN OF A MOBILITY-SUPPORT
SWITCH / 353 12.5.2 PERFORMANCE / 358 REFERENCES / 362 13 IP ROUTE
LOOKUPS 365 13.1 IP ROUTER DESIGN / 366 13.1.1 ARCHITECTURES OF GENERIC
ROUTERS / 366 13.1.2 IP ROUTE LOOKUP DESIGN / 368 13.2 IP ROUTE LOOKUP
BASED ON CACHING TECHNIQUE / 369 13.3 IP ROUTE LOOKUP BASED ON STANDARD
TRIE STRUCTURE / 369 13.4 PATRICIA TREE / 372 13.5 SMALL FORWARDING
TABLES FOR FAST ROUTE LOOKUPS / 373 13.5.1 LEVEL 1 OF DATA STRUCTURE /
374 13.5.2 LEVELS 2 AND 3 OF DATA STRUCTURE / 376 13.5.3 PERFORMANCE /
377 13.6 ROUTE LOOKUPS IN HARDWARE AT MEMORY ACCESS SPEEDS / 377 13.6.1
THE DIR-24-8-BASIC SCHEME / 378 13.6.2 PERFORMANCE / 381 13.7 IP LOOKUPS
USING MULTIWAY SEARCH / 381 13.7.1 ADAPTING BINARY SEARCH FOR BEST
MATCHING PREFIX / 381 13.7.2 PRECOMPUTED 16-BIT PREFIX TABLE / 384
13.7.3 MULTIWAY BINARY SEARCH: EXPLOITING THE CACHE LINE / 385 13.7.4
PERFORMANCE / 388 13.8 IP ROUTE LOOKUPS FOR GIGABIT SWITCH ROUTERS / 388
13.8.1 LOOKUP ALGORITHMS AND DATA STRUCTURE CONSTRUCTION / 388 13.8.2
PERFORMANCE / 395 13.9 IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE / 396
13.9.1 IP ROUTE LOOKUP ALGORITHM / 397 13.9.2 PREFIX UPDATE ALGORITHMS /
398 13.9.3 PERFORMANCE / 403 REFERENCES / 404 XII CONTENTS APPENDIX
SONET AND ATM PROTOCOLS 407 A.1 ATM PROTOCOL REFERENCE MODEL / 409 A.2
SYNCHRONOUS OPTICAL NETWORK (SONET) / 410 A.2.1 SONET SUBLAYERS / 410
A.2.2 STS-N SIGNALS / 412 A.2.3 SONET OVERHEAD BYTES / 414 A.2.4
SCRAMBLING AND DESCRAMBLING / 417 A.2.5 FREQUENCY JUSTIFICATION / 418
A.2.6 AUTOMATIC PROTECTION SWITCHING (APS) / 419 A.2.7 STS-3 VERSUS
STS-3C / 421 A.2.8 OC-N MULTIPLEXER / 422 A.3 SUB-LAYER FUNCTIONS IN
REFERENCE MODEL / 423 A.4 ASYNCHRONOUS TRANSFER MODE (ATM) / 425 A.4.1
VIRTUAL PATH/VIRTUAL CHANNEL IDENTIFIER (VPI/VCI) / 426 A.4.2 PAYLOAD
TYPE IDENTIFIER (PTI) / 427 A.4.3 CELL LOSS PRIORITY (CLP) / 428 A.4.4
PRE-DEFINED HEADER FIELD VALUES / 428 A.5 ATM ADAPTATION LAYER (AAL) /
429 A.5.1 AAL TYPE 1 (AAL1) / 431 A.5.2 AAL TYPE 2 (AAL2) / 433 A.5.3
AAL TYPES 3/4 (AAL3/4) / 434 A.5.4 AAL TYPE 5 (AAL5) / 436 REFERENCES /
438 INDEX 439
|
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| id | DE-604.BV014620198 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:04:28Z |
| institution | BVB |
| isbn | 0471004545 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009936630 |
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| owner | DE-M347 |
| owner_facet | DE-M347 |
| physical | XVI, 459 S. graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Wiley |
| record_format | marc |
| series2 | A Wiley-Interscience publication |
| spelling | Chao, H. Jonathan Verfasser aut Broadband packet switching technologies a practical guide to ATM switches and IP routers H. Jonathan Chao ; Cheuk H. Lam ; Eiji Oki New York [u.a.] Wiley 2001 XVI, 459 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier A Wiley-Interscience publication Switching Kommunikationstechnik (DE-588)4410054-1 gnd rswk-swf ATM (DE-588)4267988-6 gnd rswk-swf Switching Kommunikationstechnik (DE-588)4410054-1 s ATM (DE-588)4267988-6 s DE-604 Lam, Cheuk H. Verfasser aut Oki, Eiji Verfasser aut GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009936630&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Chao, H. Jonathan Lam, Cheuk H. Oki, Eiji Broadband packet switching technologies a practical guide to ATM switches and IP routers Switching Kommunikationstechnik (DE-588)4410054-1 gnd ATM (DE-588)4267988-6 gnd |
| subject_GND | (DE-588)4410054-1 (DE-588)4267988-6 |
| title | Broadband packet switching technologies a practical guide to ATM switches and IP routers |
| title_auth | Broadband packet switching technologies a practical guide to ATM switches and IP routers |
| title_exact_search | Broadband packet switching technologies a practical guide to ATM switches and IP routers |
| title_full | Broadband packet switching technologies a practical guide to ATM switches and IP routers H. Jonathan Chao ; Cheuk H. Lam ; Eiji Oki |
| title_fullStr | Broadband packet switching technologies a practical guide to ATM switches and IP routers H. Jonathan Chao ; Cheuk H. Lam ; Eiji Oki |
| title_full_unstemmed | Broadband packet switching technologies a practical guide to ATM switches and IP routers H. Jonathan Chao ; Cheuk H. Lam ; Eiji Oki |
| title_short | Broadband packet switching technologies |
| title_sort | broadband packet switching technologies a practical guide to atm switches and ip routers |
| title_sub | a practical guide to ATM switches and IP routers |
| topic | Switching Kommunikationstechnik (DE-588)4410054-1 gnd ATM (DE-588)4267988-6 gnd |
| topic_facet | Switching Kommunikationstechnik ATM |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009936630&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT chaohjonathan broadbandpacketswitchingtechnologiesapracticalguidetoatmswitchesandiprouters AT lamcheukh broadbandpacketswitchingtechnologiesapracticalguidetoatmswitchesandiprouters AT okieiji broadbandpacketswitchingtechnologiesapracticalguidetoatmswitchesandiprouters |