Testing of digital systems:
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| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Cambridge [u.a.]
Cambridge Univ. Press
2003
|
| Edition: | 1. publ. |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XVI, 1000 S. zahlr. graph. Darst. |
| ISBN: | 0521773563 |
Staff View
MARC
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| 100 | 1 | |a Jha, Niraj K. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Testing of digital systems |c N. K. Jha and S. Gupta |
| 250 | |a 1. publ. | ||
| 264 | 1 | |a Cambridge [u.a.] |b Cambridge Univ. Press |c 2003 | |
| 300 | |a XVI, 1000 S. |b zahlr. graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Digital integrated circuits |x Testing | |
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| 856 | 4 | 2 | |m Digitalisierung UB Passau |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009924518&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009924518 | |
Record in the Search Index
| _version_ | 1806054168380571648 |
|---|---|
| adam_text |
Contents
Preface
List of gate symbols
page
xiii
xvi
Introduction
by Ad van
de Goor
1.1
Faults and their manifestation
1.2
An analysis of faults
1.3
Classification of tests
1.4
Fault coverage requirements
1.5
Test economics
1
3
11
14
16
Fault models
26
2.1
Levels of abstraction in circuits
2.2
Fault models at different abstraction levels
2.3
Inductive fault analysis
2.4
Relationships among fault models
26
28
41
44
Combinational logic and fault simulation
3.1
Introduction
3.2
Preliminaries
3.3
Logic simulation
3.4
Fault simulation essentials
3.5
Fault simulation paradigms
3.6
Approximate, low-complexity fault simulation
49
49
52
64
75
82
120
Test generation for combinational circuits
134
4.1
Introduction
134
4.2
Composite circuit representation and value systems
136
4.3
Test generation basics
147
4.4
Implication
153
4.5
Structural test generation: preliminaries
180
4.6
Specific structural test generation paradigms
197
4.7
Non-structural test generation techniques
223
4.8
Test generation systems
235
4.9
Test generation for reduced heat and noise during test
250
Appendix 4.A Implication procedure
262
Sequential ATPG
266
5.1
Classification of sequential ATPG methods and faults
266
5.2
Fault collapsing
273
5.3
Fault simulation
277
5.4
Test generation for synchronous circuits
285
5.5
Test generation for asynchronous circuits
303
5.6
Test compaction
306
/ddq testing
314
314
316
328
333
340
342
6.7
Economics of /ddq testing
348
■
Functional testing
356
6.1
Introduction
6.2
Combinational ATPG
6.3
Sequential ATPG
6.4
Fault diagnosis of combinational circuits
6.5
Built-in current sensors
6.6
Advanced concepts in current sensing based
testin
7.1
Universal test sets
356
7.2
Pseudoexhaustive
testing
359
7.3
Iterative logic array testing
366
8
Delay
fault
testing
8.1
Introduction
8.2
Combinational test generation
8.3
Combinational fault simulation
8.4
Combinational delay fault diagnosis
8.5
Sequential test generation
8.6
Sequential fault simulation
8.7
Pitfalls in delay fault testing and some remedies
8.8
Unconventional delay fault testing techniques
CMOS testing
9.1
Testing of dynamic CMOS circuits
9.2
Testing of static CMOS circuits
9.3
Design for robust testability
■
10
Fault diagnosis
10.1
Introduction
10.2
Notation and basic definitions
10.3
Fault models for diagnosis
10.4
Cause-effect diagnosis
10.5
Effect-cause diagnosis
10.6
Generation of vectors for diagnosis
■
11
Design for testability
11.1
Introduction
11.2
Scan design
11.3
Partial scan
11.4
Organization and use of scan chains
11.5
Boundary scan
11.6
DFT for other test objectives
12
Built-in self-test
680
12.1
Introduction
680
12.2
Pattern generators
682
12.3
Estimation of test length
697
12.4
Test points to improve testability
708
12.5
Custom pattern generators for a given circuit
715
12.6
Response compression
729
12.7
Analysis of aliasing in linear compression
738
12.8
BIST methodologies
745
12.9
In-situ BIST methodologies
755
12.10
Scan-based BIST methodologies
769
12.11
BIST for delay fault testing
775
12.12
BIST techniques to reduce switching activity
780
Synthesis for testability
799
13.1
Combinational logic synthesis for stuck-at fault testability
799
13.2
Combinational logic synthesis for delay fault testability
819
13.3
Sequential logic synthesis for stuck-at fault testability
829
13.4
Sequential logic synthesis for delay fault testability
836
Memory testing
845
by Ad van
de Goor
14.1
Motivation for testing memories
845
14.2
Modeling memory chips
846
14.3
Reduced functional faults
852
14.4
Traditional tests
864
14.5
March tests
868
14.6
Pseudorandom memory tests
878
15
High-level test synthesis
893
15.1
Introduction
893
15.2 RTL
test generation
894
15.3 RTL
fault simulation
912
15.4 RTL
design
for testability
914
15.5 RTL
built-in self-test
929
15.6
Behavioral modification for testability
937
15.7
Behavioral synthesis for testability
939
16
System-on-a-chip test synthesis
953
16.1
Introduction
953
16.2
Core-level test
954
16.3
Core test access
955
16.4
Core test wrapper
977
Index
983 |
| any_adam_object | 1 |
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| author_facet | Jha, Niraj K. Gupta, Sandeep |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| illustrated | Illustrated |
| indexdate | 2024-07-31T00:57:54Z |
| institution | BVB |
| isbn | 0521773563 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009924518 |
| oclc_num | 248172068 |
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| owner | DE-824 DE-739 |
| owner_facet | DE-824 DE-739 |
| physical | XVI, 1000 S. zahlr. graph. Darst. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Cambridge Univ. Press |
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| spelling | Jha, Niraj K. Verfasser aut Testing of digital systems N. K. Jha and S. Gupta 1. publ. Cambridge [u.a.] Cambridge Univ. Press 2003 XVI, 1000 S. zahlr. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Digital integrated circuits Testing Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 s Test (DE-588)4059549-3 s DE-604 Gupta, Sandeep Verfasser aut Digitalisierung UB Passau application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009924518&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Jha, Niraj K. Gupta, Sandeep Testing of digital systems Digital integrated circuits Testing Digitale integrierte Schaltung (DE-588)4113313-4 gnd Test (DE-588)4059549-3 gnd |
| subject_GND | (DE-588)4113313-4 (DE-588)4059549-3 |
| title | Testing of digital systems |
| title_auth | Testing of digital systems |
| title_exact_search | Testing of digital systems |
| title_full | Testing of digital systems N. K. Jha and S. Gupta |
| title_fullStr | Testing of digital systems N. K. Jha and S. Gupta |
| title_full_unstemmed | Testing of digital systems N. K. Jha and S. Gupta |
| title_short | Testing of digital systems |
| title_sort | testing of digital systems |
| topic | Digital integrated circuits Testing Digitale integrierte Schaltung (DE-588)4113313-4 gnd Test (DE-588)4059549-3 gnd |
| topic_facet | Digital integrated circuits Testing Digitale integrierte Schaltung Test |
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