SOC design methodologies: IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic Publishers
2002
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| Schriftenreihe: | International Federation for Information Processing
90 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Includes bibliographical references and indexes |
| Beschreibung: | xvi, 477 p. ill. : 25 cm |
| ISBN: | 1402071485 |
Internformat
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| 245 | 1 | 0 | |a SOC design methodologies |b IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France |c edited by Michel Robert ... [et al.] |
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Datensatz im Suchindex
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| adam_text | SOC DESIGN METHODOLOGIES IFIPTC10/WG10.5 ELEVENTH INTERNATIONAL
CONFERENCE ON VERY LARGE SCALE INTEGRATION OF SYSTEMS-ON-CHIP
(VLSI-SOC07) DECEMBER 3-5, 2001, MONTPELLIER, FRANCE EDITED BY MICHEL
ROBERT BRUNO ROUZEYRE CHRISTIAN PIGUET MARIE-USE FLOTTES LABORATOIRE
D LNFORMATIQUE DE ROBOTIQUE ET DE MICROELECTRONIQUE DE MONTPELLIER
(LIRMM) UMR CNRS/UNIVERSITE MONTPELLIER II 1 1 J) LI FRANCE L 1 K M
KLUWER ACADEMIC PUBLISHERS BOSTON / DORDRECHT/ LONDON CONTENTS PREFACE
IX CONFERENCE COMMITTEES XIII ARCHITECTURE FOR SIGNAL & IMAGE PROCESSING
TWO ASIC FOR LOW AND MIDDLE LEVELS OF REAL TIME IMAGE 3 PROCESSING P.
LAMATY, B. MAZAR, D. DEMIGNY, L. KESSAL, M. KARABERNOU 64 X 64 PIXELS
GENERAL PURPOSE DIGITAL VISION CHIP 15 T. KOMURO, M. ISHIKAWA A VISION
SYSTEM ON CHIP FOR INDUSTRIAL CONTROL 27 E. SENN, E. MARTIN FAST
RECURSIVE IMPLEMENTATION OF THE GAUSSIAN FILTER 39 D. DEMIGNY, L.
KESSAL, J. PONS DYNAMICALLY RE-CONFIGURABLE ARCHITECTURES A DYNAMICALLY
RECONFIGURABLE ARCHITECTURE FOR LOW-POWER 51 MULTIMEDIA TERMINALS R.
DAVID, D. CHILLET, S. PILLEMENT, O. SENTIEYS DYNAMICALLY RECONFIGURABLE
ARCHITECTURES FOR DIGITAL 63 SIGNAL PROCESSING APPLICATIONS G.
SASSATELLI, L. TORRES, P. BENOIT, G. CAMBON, M. ROBERT, J. GALY
RECONFIGURABLE ARCHITECTURE USING HIGH SPEED FPGA 75 L. KESSAL, R.
BOURGUIBA, D. DEMIGNY, N. BOUDOUANI, M. KARABERNOU VI CONTENTS CAD TOOLS
DESIGN TECHNOLOGY FOR SYSTEMS-ON-CHIP 87 R. CAMPOSANO, D. MACMILLEN
DISTRIBUTED COLLABORATIVE DESIGN OVER CAVE2 FRAMEWORK 97 L. S.
INDRUSIAK, J. BECKER, M. GLESNER, R. REIS HIGH PERFORMANCE JAVA HARDWARE
ENGINE AND SOFTWARE 109 KERNEL FOR EMBEDDED SYSTEMS M. H. MIKI, M.
KIMURA, T. ONOYE, I. SHIRAKAWA AN OBJECT-ORIENTED METHODOLOGY FOR
MODELING THE PRECISE 121 BEHAVIOR OF PROCESSOR ARCHITECTURES /. C.
OTERO, F. R. WAGNER INTERCONNECT CAPACITANCE MODELLING IN A VDSM CMOS
TECHNOLOGY 133 D. BERNARD, C. LANDRAULT, P. NOUET IP DESIGN & REUSE
ABSTRACT COMMUNICATION MODEL AND AUTOMATIC INTERFACE 145 GENERATION FOR
IP INTEGRATION IN HARDWARE/SOFTWARE CO-DESIGN C. ARAUJO, E. BARROS AN
EVOLUTIONARY APPROACH FOR PARETO-OPTIMAL CONFIGURATIONS 157 IN SOC
PLATFORMS G. ASCIA, V. CATANIA, M. PALESI DESIGN OF A BRANCH-BASED
CARRY-SELECT ADDER IP PORTABLE 169 IN 0.25 /XM BULK AND
SILICON-ON-INSULATOR CMOS TECHNOLOGIES A. NEVE, D. FLANDRE HIGH LEVEL
DESIGN METHODOLOGIES A STANDARDIZED CO-SIMULATION B ACKBONE 181 B. A. DE
MELLO, F. R. WAGNER AUTOMATIC CODE-TRANSFORMATION AND ARCHITECTURE
REFINEMENT 193 FOR APPLICATION-SPECIFIC MULTIPROCESSOR SOCS WITH SHARED
MEMORY S. MEFTALI, F. GHARSALLI, F. ROUSSEAU, A. A. JERRAYA CONTENTS VII
POWER ISSUES MODELING POWER DYNAMICS FOR AN EMBEDDED DSP PROCESSOR 205
CORE. AN EMPIRICAL MODEL C.H. GEBOTYS, R. MURESAN POWER CONSUMPTION
MODEL FOR THE DSP OAK PROCESSOR 217 P. GUITTON-OUHAMOU, C. BELLEUDY, M.
AUGUIN DESIGN FOR SPECIFIC CONSTRAINTS INTEGRATION OF ROBUSTNESS IN THE
DESIGN OF A CELL 229 J.M. DUTERTRE, F.M. ROCHE, G. CATHEBRAS IMPACT OF
TECHNOLOGY SPREADING ON MEMS DESIGN ROBUSTNESS 241 V. BEROULLE, L.
LATORRE, M. DARDALHON, C. OUDEA, G. PEREZ, F. PRESSECQ, P. NOUET
ARCHITECTURES A NEW EFFICIENT VLSI ARCHITECTURE FOR FULL SEARCH BLOCK
253 MATCHING MOTION ESTIMATION N. ROMA, L. SOUSA DESIGN CONSIDERATIONS
OF A LOW-COMPLEXITY, LOW-POWER INTEGER 265 TURBO DECODER S. M. PISUK, P.
H. WU LOW POWER, LOW VOLTAGE LOW-VOLTAGE EMBEDDED-RAM TECHNOLOGY:
PRESENT AND FUTURE 277 K. ITOH, H. MIZUNO LOW-VOLTAGE 0,25 FIM CMOS
IMPROVED POWER ADAPTIVE ISSUE 289 QUEUE FOR EMBEDDED MICROPROCESSORS B.
CURRAN, M. GIFALDI, J. MARTIN, A. BUYUKTOSUNOGLU, M. MARGALA, D.
ALBONESI GATE SIZING FOR LLAW POWER DESIGN 301 P. MAURINE, N. AZEMARD,
D. AUVERGNE TIMING ISSUES MODELING AND DESIGN OF ASYNCHRONOUS PRIORITY
ARBITERS FOR 313 ON-CHIP COMMUNICATION SYSTEMS J-B. RIGAUD, J. QUARTANA,
L. FESQUET, M. RENAUDIN FEASIBLE DELAY BOUND DEFINITION 325 N. AZEMARD,
M. ALINE, P. MAURINE, D. AUVERGNE VIII CONTENTS ADVANCE IN MIXED SIGNAL
CMOS MIXED-SIGNAL CIRCUITS DESIGN ON A DIGITAL ARRAY USING 337 MINIMUM
TRANSISTORS J. H. CHOI, S. BAMPI A VHDL-AMS CASE STUDY: THE INCREMENTAL
DESIGN OF AN EFFICIENT 349 3 RD GENERATION MOS MODEL OF A DEEP SUB
MICRON TRANSISTOR C. LALLEMENT, F. PECHEUX, Y. HERVE VERIFICATION &
VALIDATION SPEEDING UP VERIFICATION OF RTL DESIGNS BY COMPUTING 361
ONE-TO-ONE ABSTRACTIONS WITH REDUCED SIGNAL WIDTHS P. JOHANNSEN, R.
DRECHSLER FUNCTIONAL TEST GENERATION USING CONSTRAINT LOGIC PROGRAMMING
375 Z. ZENG, M. CIESIELSKI, B. ROUZEYRE TEST AN INDUSTRIAL APPROACH TO
CORE-BASED SYSTEM CHIP TESTING 389 E. J. MARINISSEN POWER-CONSTRAINED
TEST SCHEDULING FOR SOCS UNDER A NO SESSION 401 SCHEME M-L. FLOTTES,
J. POUGET, B. ROUZEYRE RANDOM ADJACENT SEQUENCES: AN EFFICIENT SOLUTION
FOR LOGIC BIST 413 R. DAVID, P. GIRARD, C. LANDRAULT, S.
PRAVOSSOUDOVITCH, A. VIRAZEL ON-CHIP GENERATOR OF A SAW-TOOTH TEST
STIMULUS FOR ADC BIST 425 F. AZAI S, S. BERNARD, Y. BERTRAND, M.
RENOVELL BUILT-IN TEST OF ANALOG NON-LINEAR CIRCUITS IN A SOC
ENVIRONMENT 437 L. CARRO, A. C R NACUL, D. JANNER, M. LUBASZEWSKI
SENSORS DESIGN OF A FAST CMOS APS IMAGER FOR HIGH SPEED LASER 449
DETECTIONS B. CASADEI, J. P. HE NORMAND, Y. HU, B. CUNIN NOISE
OPTIMISATION OF A PIEZORESISTIVE CMOS MEMS FOR MAGNETIC 461 FIELD
SENSING V. BEROULLE, Y. BERTRAND, L. LATORRE, P. NOUET AUTHORS INDEX 473
KEYWORDS INDEX 475
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| spelling | IFIP TC10/WG10.5 International Conference on Very Large Scale Integration of Systems-on-Chip 11 2001 Montpellier Verfasser (DE-588)16139182-5 aut SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France edited by Michel Robert ... [et al.] Boston Kluwer Academic Publishers 2002 xvi, 477 p. ill. : 25 cm txt rdacontent n rdamedia nc rdacarrier International Federation for Information Processing 90 Includes bibliographical references and indexes (DE-588)1071861417 Konferenzschrift gnd-content Robert, Michel Sonstige oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009899183&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France |
| subject_GND | (DE-588)1071861417 |
| title | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France |
| title_auth | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France |
| title_exact_search | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France |
| title_full | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France edited by Michel Robert ... [et al.] |
| title_fullStr | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France edited by Michel Robert ... [et al.] |
| title_full_unstemmed | SOC design methodologies IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France edited by Michel Robert ... [et al.] |
| title_short | SOC design methodologies |
| title_sort | soc design methodologies ifip tc10 wg10 5 eleventh international conference on very large scale integration of systems on chip vlsi soc 01 december 3 5 2001 montpellier france |
| title_sub | IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France |
| topic_facet | Konferenzschrift |
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