IC mask design: essential layout techniques
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
McGraw-Hill
2002
|
| Schriftenreihe: | McGraw-Hill professional engineering
|
| Schlagworte: | |
| Online-Zugang: | Table of contents Inhaltsverzeichnis |
| Beschreibung: | XVIII, 457 S. graph. Darst. |
| ISBN: | 0071389962 |
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Datensatz im Suchindex
| _version_ | 1809403460701913088 |
|---|---|
| adam_text |
IC MASK DESIGN ESSENTIAL LAYOUT TECHNIQUES CHRISTOPHER SAINT JUDY SAINT
MCGRAW-HILL NEW YORK | CHICAGO | SAN FRANCISCO | LISBON | LONDON |
MADRID MEXICO CITY | MILAN | NEW DELHI | SAN JUAN | SEOUL SINGAPORE |
SYDNEY | TORONTO CONTENTS INTRODUCTION XIII ACKNOWLEDGMENTS XV OPEN
LETTER TO CIRCUIT DESIGNERS XVII CHAPTER 1 DIGITAL LAYOUT 1 CHAPTER
PREVIEW 1 OPENINGTHOUGHTS ON DIGITAL LAYOUT 1 DESIGN PROCESS 2 VERIFYING
THE CIRCUITRY LOGIC 2 COMPILING A NETLIST 3 DRIVE STRENGTH 4 CLOCK TREE
SYNTHESIS 5 LAYOUT PROCESS 7 FLOORPLANNING 7 BLOCK PLACEMENT 7 GATE
GROUPING 8 BLOCK LEVEL CONNECTIVITY 8 USING FLYLINES 9 TIMING CHECKS 10
PLACEMENT 11 I/ODRIVERS 12 ROUTING 13 POWER NETS 13 STRAPPING 14 CLOCK
NET WIRING 15 OTHER CRITICAL NETS 16 REMAINING NETS 16 FINISHING THE
WIRING BY HAND 17 PREFABRICATED GATE ARRAY CHIPS 18 VERIFICATION 19
DESIGN VERIFICATION 19 PHYSICAL VERIFICATION 20 VI | CONTENTS GDSIIFILE
DRC AND LVS CHECKS LIBRARY MANAGEMENT SUMMARY AND FLOWCHART CLOSURE ON
DIGITAL LAYOUT HERE'S WHAT WE'VE LEARNED 20 20 21 22 23 24 CHAPTER 2
STANDARD CELL TECHNIQUES 25 CHAPTER PREVIEW OPENINGTHOUGHTS ON STANDARD
CELL TECHNIQUES STANDARDIZED GRIDS GRID-BASED SYSTEMS DETERMINING GRID
SIZE RULE-BASED ROUTERS DIRECTIONAL LAYER TECHNIQUE LIBRARY RULES FOR
GRID-BASED SYSTEMS INPUT AND OUTPUT ALIGNMENT FIXED HEIGHT, VARIABLE
WIDTH DETERMINING WIRE GAUGE COMMON N WELL HALF-GRID CELL SIZING HALF
DESIGN RULE ROUTING CHANNELS CHANNEL ROUTERS ANTENNA RULES STANDARDIZED
INPUT AND OUTPUT CELLS USINGSTANDARDIZATION IN ANALOG MASK DESIGN
CLOSURE ON STANDARD CELL TECHNIQUES HERE'S WHAT WE'VE LEARNED 25 25 26
26 26 28 29 32 32 34 35 35 37 38 39 43 45 45 46 47 48 CHAPTER 3 ANALOG
LAYOUT 49 CHAPTER PREVIEW 49 OPENING THOUGHTS ON ANALOG LAYOUT 49
DIGITAL SKILLS VS. ANALOG SKILLS 50 DIFFERENCE OF SCALE 50 DIFFERENCE
OFPRIMARY OBJECTIVE 51 DIFFERENCE OF TEAMWORK 51 DIFFERENCE OF
COMPLETION SCHEDULE 52 DIFFERENCE OF INNOVATION 52 DIFFERENCE OF
CONSTRAINTS 52 DIFFERENCE OF UNDERSTANDING CIRCUIT TECHNIQUES 53 THREE
KEY QUESTIONS 53 CONTENTS | VII QUESTION 1: WHAT DOES THIS CIRCUIT DO?
55 QUESTION 2: HOW MUCH CURRENT DOES IT TAKE? 56 CALCULATING CURRENT
DENSITIES 57 QUESTION 2A: WHERE ARE THE HIGH AND LOW CURRENT PATHS? 58
DEVICE ORIENTATION 59 QUESTION 3: WHAT MATCHING REQUIREMENTS ARE THERE?
64 ADDITIONAL QUESTIONS 64 BIPOLAR ANALOG 65 EXPECTATIONS OF AN ANALOG
MASK DESIGNER 66 CLOSURE ON ANALOG LAYOUT 70 HERE'S WHAT WE'VE LEARNED
70 APPENDIX: KEY QUESTIONS DISCUSSION 71 CHAPTER 4 PARASITICS 79 CHAPTER
PREVIEW OPENINGTHOUGHTS ON PARASITICS PARASITIC CAPACITANCE WIRE LENGTH
METAL SELECTION METAL OVER METAL PARASITIC RESISTANCE CALCULATING IR
DROPS WIRING OPTIONS PARASITIC INDUCTANCE DEVICE PARASITICS CMOS
TRANSISTOR EXAMPLE BIPOLAR TRANSISTOR EXAMPLE FUELL CUSTOM OPTIONS
CLOSURE ON PARASITICS HERE'S WHAT WE'VE LEARNED 79 79 80 81 82 84 86 86
88 91 92 92 93 94 94 95 CHAPTER 5 MATCHING 97 CHAPTER PREVIEW
OPENINGTHOUGHTS ON MATCHING IMPORTANCE OF LAYOUT IMPORTANCE OF
COMMUNICATION SIMPLE MATCHING ROOT DEVICE METHOD INTERDIGITATING DEVICES
DUMMY DEVICES COMMON CENTROID 97 97 98 100 100 103 105 108 109 VIII |
CONTENTS CROSS-QUADING SYMMETRY MATCHING SIGNAL PATHS DEVICE SIZE
CHOICES CLOSURE ON MATCHING HERE'S WHAT WE'VE LEARNED RULES OF MATCHING
110 113 114 117 119 120 120 CHAPTER 6 NOISE ISSUES 121 CHAPTER PREVIEW
OPENINGTHOUGHTS ON NOISE ISSUES NOISY NEIGHBORS COMMON SENSE NOISE
SOLUTIONS TURN DOWN THE VOLUME ROCK BAND MOVES INSIDE THEIR HOUSE GO
INSIDE YOUR OWN HOUSE CLOSE ALL WINDOWS CALL THE SHERIFF MOVE TO A NEW
NEIGHBORHOOD WIRE SOLUTIONS COAXIAL SHIELDING DIFFERENTIAL SIGNALS
DECOUPLED POWER RAILS STACKED POWER RAILS HARMONIE INTERFERENCE CLOSURE
ON NOISE ISSUES HERE'S WHAT WE'VE LEARNED 121 121 122 124 124 125 128
128 128 129 130 130 132 134 135 136 139 139 CHAPTER 7 FLOORPLANNING 141
CHAPTER PREVIEW OPENINGTHOUGHTS ON FLOORPLANNING PRIMARY DRIVERS OF
FLOORPLANNING PIN-DRIVEN PLANNING EFFECT OFPIN PLACEMENT ESD SUPPLY
STRATEGIES BLOCK-DRIVEN PLANNING SIGNAL-DRIVEN PLANNING RESHAPING BLOCKS
SIZING ESTIMATES LEAVING ENOUGH ROOM ESTIMATING WITH EXISTING CIRCUITRY
CLOSURE ON FLOORPLANNING HERE'S WHAT WE'VE LEARNED 141 141 142 143 143
145 149 152 153 155 155 158 159 160 CONTENTS | IX CHAPTER 8 GENERAL
TECHNIQUES 161 CHAPTER PREVIEW 161 GENERAL TECHNIQUES 161 #1 PICK FIVE
OR SIX NON-MINIMUM DESIGN RULES 162 #2 GET THEE TO THE LOWEST PARASITIC
METAL 165 #3 PLENTY OF WIDE WIRING AND VIAS 165 #4 DON'T BELIEVE YOUR
CIRCUIT DESIGNER 167 #5 USE A CONSISTENT ORIENTATION 168 #6 DON'T GO
OVERBOARD 169 #7 KEEP OFF THE BLOCKS 169 #8 CARE FOR YOUR SENSITIVE AND
NOISY SIGNALS EARLY 170 #9 IF IT LOOKS NICE, IT WILL WORK 170 #10 LEARN
YOUR PROCESS 171 #11 DON'T LET NOISE FIND THE SUBSTRATE 172 # 12 SPREAD
YOUR SPINACH AROUND YOUR DINNER PLATE 172 #13 COPY AND RENAME CELLS
BEFORE MAKING CHANGES 175 #14 REMEMBER YOUR HIERARCHY LEVEL 176 #15
BUILD-IN EASY METAL REVISIONS 177 #16 DRAW BIG POWER BUSES 182 #17 BREAK
UP LARGE CIRCUITS 184 CLOSURE ON GENERAL TECHNIQUES 184 ANCIENT SECRETS
OF MASK DESIGN 185 CHAPTER 9 PACKAGING 187 CHAPTER PREVIEW
OPENINGTHOUGHTS ON PACKAGING BONDING METHODS ULTRASONIC WEDGE BONDING
ULTRASONIC BALL BONDING FLIP CHIP TECHNOLOGY MULTI-TIER PACKAGING ISSUES
IN PACKAGING OVERALL APPEARANCE 45-DEGREE RULE MINIMAL SILICON OVERLAP
WIRE LENGTH PAED DISTRIBUTION SIZING ESTIMATES PAD-LIMITED DESIGN
CORE-LIMITED DESIGN PACKAGE MAXIMUM CHECK FINAL DIE SIZE CALCULATIONS
FILLING PAED GAPS CLOSURE ON PACKAGING HERE'S WHAT WE'VE LEARNED 187 187
188 189 190 191 192 193 193 194 195 195 196 197 197 199 200 200 206 207
208 X | CONTENTS CHAPTER 10 VERIFICATION 209 CHAPTER PREVIEW OPENING
THOUGHTS ON VERIFICATION CHECKING SOFTWARE DESIGN RULE CHECK (DRC)
BOOLEAN COMMAND LINES AND FUNCTION OR FUNCTION NOT FUNCTION RULE
CHECKING COMMAND LINES LAYOUT VERSUS SCHEMATIC (LVS) NETLISTS PROBLEM
SOLVING 1. CHECK NUMBER OF DEVICES 2. CHECK TYPES OF DEVICES 3. CHECK
NUMBER OF NETS 4. SOLVING COMPLEX NET PROBLEMS A. POWER SUPPLIES B.
NAMED NETS 5. DON'T TRUST YOUR CIRCUIT DESIGNER 6. CHECK FOR POSSIBLE
SWAPPING OVER 7. CHECK FOR A TOP LEVEL SHORT 8. CHECK FOR NINJA
INVISIBILITY 9. KNOW YOUR CIRCUITS 10. LET OTHERS HELP CLOSURE ON
VERIFICATION HERE'S WHAT WE'VE LEARNED CHAPTER 11 DATA FORMATS CHAPTER
PREVIEW OPENINGTHOUGHTS ON DATA FORMATS INDUSTRY STANDARD DATABASE
FORMATS HEADER INFORMATION COORDINATING RESOLUTIONS PATTERN GENERATION
KNOW YOUR GRIDS CLOSURE ON DATA FORMATS HERE'S WHAT WE'VE LEARNED CASE
STUDY #1 CMOS AMPLIFIER 209 209 210 211 211 212 214 215 218 220 221 222
222 223 224 226 226 228 229 230 232 232 233 234 234 235 237 237 237 238
238 238 241 242 243 243 247 THE NEW JOB ASSIGNMENT BILL REASONS HIS
FLOORPLAN BILL THINKS THROUGH HIS LAYOUT 247 255 259 CONTENTS | XI TED
RETURNS 272 BILL RETHINKS 280 THE CHIP IS ASSEMBLED 304 PACKAGING 325
APPENDIX 326 CASE STUDY #2 BIPOLAR MIXER 341 INTRODUCTION TO CASE STUDY
2 THE ASSIGNMENT "WHAT DOES THE CIRCUIT DO?" "WHAT ARE THE CIRCUIT
REQUIREMENTS?" BIPOLAR TRANSISTOR REVIEW FIRST LAYOUT INITIAL OVERVIEW
CURRENT SOURCE TRANSISTORS RESISTORS LOWER PAIR EMITTERS BASES
COLLECTORS UPPER QUAD EMITTERS BASES COLLECTORS LOADS OUTPUT RESISTORS
ANALYSIS OF FIRST LAYOUT BIPOLAR TRANSISTOR LAYOUT*WRAP-AROUND TECHNIQUE
SECOND LAYOUT CURRENT SOURCE EMITTERS BASES COLLECTORS RESISTORS LOWER
PAIR INTERDIGITATION PLAN EMITTERS COLLECTORS BASES INPUTS UPPER QUAD
INTERDIGITATION PLAN 341 342 342 345 345 346 346 349 349 349 351 352 353
354 355 355 357 358 358 358 361 362 362 365 365 367 368 368 368 370 370
371 371 373 373 375 375 XUE | CONTENTS EMITTERS COLLECTORS BASES INPUTS
LOADS INTERDIGITATION PLAN RESISTORS OUTPUTS ANALYSIS OF SECOND LAYOUT
THIRD LAYOUT LOWER PAIR CROSS-QUADING PLAN EMITTERS COLLECTORS BASES
INPUTS FINAL ANALYSIS COMPARISON OF CASE STUDY 1 AND CASE STUDY 2
BEGLNNINGS THE FOUR ENGINEERS OUTTAKES CONTACT US SUGGESTED READINGS AND
RESOURCES EDUCATIONAL PROGRAMS GLOSSARY INDEX 376 377 377 380 380 380
382 383 384 385 386 387 387 388 388 390 393 393 395 409 411 415 417 419
421 445 |
| any_adam_object | 1 |
| author | Saint, Christopher |
| author_facet | Saint, Christopher |
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| author_sort | Saint, Christopher |
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| dewey-search | 621.3815 |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| indexdate | 2024-09-06T00:13:27Z |
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| isbn | 0071389962 |
| language | English |
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| physical | XVIII, 457 S. graph. Darst. |
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| publisher | McGraw-Hill |
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| spelling | Saint, Christopher Verfasser aut IC mask design essential layout techniques Christopher Saint ; Judy Saint New York [u.a.] McGraw-Hill 2002 XVIII, 457 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier McGraw-Hill professional engineering Integrated circuit layout Integrated circuits Masks Design and construction Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Maske Halbleitertechnologie (DE-588)4282533-7 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Maske Halbleitertechnologie (DE-588)4282533-7 s Layout Mikroelektronik (DE-588)4264372-7 s DE-604 Saint, Judy Sonstige oth http://www.loc.gov/catdir/toc/mh021/2002021280.html Table of contents GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009875075&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Saint, Christopher IC mask design essential layout techniques Integrated circuit layout Integrated circuits Masks Design and construction Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Maske Halbleitertechnologie (DE-588)4282533-7 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4264372-7 (DE-588)4282533-7 |
| title | IC mask design essential layout techniques |
| title_auth | IC mask design essential layout techniques |
| title_exact_search | IC mask design essential layout techniques |
| title_full | IC mask design essential layout techniques Christopher Saint ; Judy Saint |
| title_fullStr | IC mask design essential layout techniques Christopher Saint ; Judy Saint |
| title_full_unstemmed | IC mask design essential layout techniques Christopher Saint ; Judy Saint |
| title_short | IC mask design |
| title_sort | ic mask design essential layout techniques |
| title_sub | essential layout techniques |
| topic | Integrated circuit layout Integrated circuits Masks Design and construction Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Maske Halbleitertechnologie (DE-588)4282533-7 gnd |
| topic_facet | Integrated circuit layout Integrated circuits Masks Design and construction Integrierte Schaltung Layout Mikroelektronik Maske Halbleitertechnologie |
| url | http://www.loc.gov/catdir/toc/mh021/2002021280.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009875075&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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