Layout optimization in VLSI design:
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Dordrecht [u.a.]
Kluwer Acad. Publ.
2001
|
| Schriftenreihe: | Network theory and applications
8 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 288 S. graph. Darst. |
| ISBN: | 1402000898 |
Internformat
MARC
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-009866542 | ||
Datensatz im Suchindex
| _version_ | 1804129284276617216 |
|---|---|
| adam_text | CONTENTS PREFACE . VII 1. INTEGRATED FLOORPLANNING AND INTERCONNECT
PLANNING .. 1 H.-M. CHC.N. MARTIN D.F. WONG, H. ZHOU.. F.Y. YOUNG, H. H.
YANG, UND N. SHERWANI 2. INTERCONNECT PLANNING 19 J. CONG 3. MODERN
STANDARD-CELL PLACEMENT TECHNIQUES 45 X. YANG, E. BOZORGZADEH, M.
SARRAFZADEH, AND M. WANG 4. NON-HANAN OPTIMIZATION FOR GLOBAL VLSI
INTERCONNECT 89 ./. HU AND S. S. SAPATNEKAR 5. TECHNIQUES FOR
TIMING-DRIVEN ROUTING 125 ./. ULLIS 6. INTERCONNECT MODELING AND DESIGN
WITH CONSIDERATION OF INDUCTANCE 155 L. HE 7. MODELING AND
CHARACTERIZATION OF IC INTERCONNECTS AND PACKAGINGS FOR THE SIGNAL
INTERGRITY VERIFICATION ON HIGH-PERFORMANCE VLSI CIRCUITS 191 Y EO 8.
TRADEOFFS IN DIGITAL BINARY ADDER DESIGN: THE EFFECTS OF FLOORPLANNING,
NUMBER OF LEVELS OF METALS, AND SUPPLY VOLTAGE ON PERFORMANCE AND AREA
261 V. KANTABIDRA. S. PERRI. AND P CORSO7I.CL.LO
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| id | DE-604.BV014429830 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T19:02:41Z |
| institution | BVB |
| isbn | 1402000898 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009866542 |
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| physical | VIII, 288 S. graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Kluwer Acad. Publ. |
| record_format | marc |
| series | Network theory and applications |
| series2 | Network theory and applications |
| spelling | Layout optimization in VLSI design ed. by Bing Lu ... Dordrecht [u.a.] Kluwer Acad. Publ. 2001 VIII, 288 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Network theory and applications 8 Integrated circuits Very large scale integration Design and construction Multidisciplinary design optimization VLSI (DE-588)4117388-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s DE-604 Lu, Bing Sonstige oth Network theory and applications 8 (DE-604)BV014100569 8 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009866542&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Layout optimization in VLSI design Network theory and applications Integrated circuits Very large scale integration Design and construction Multidisciplinary design optimization VLSI (DE-588)4117388-0 gnd Entwurf (DE-588)4121208-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4121208-3 |
| title | Layout optimization in VLSI design |
| title_auth | Layout optimization in VLSI design |
| title_exact_search | Layout optimization in VLSI design |
| title_full | Layout optimization in VLSI design ed. by Bing Lu ... |
| title_fullStr | Layout optimization in VLSI design ed. by Bing Lu ... |
| title_full_unstemmed | Layout optimization in VLSI design ed. by Bing Lu ... |
| title_short | Layout optimization in VLSI design |
| title_sort | layout optimization in vlsi design |
| topic | Integrated circuits Very large scale integration Design and construction Multidisciplinary design optimization VLSI (DE-588)4117388-0 gnd Entwurf (DE-588)4121208-3 gnd |
| topic_facet | Integrated circuits Very large scale integration Design and construction Multidisciplinary design optimization VLSI Entwurf |
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