Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
2002
|
| Ausgabe: | 2. ed., 3. printing |
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references (p. [247]-254) and index |
| Beschreibung: | XXIII, 281 S. graph. Darst. |
| ISBN: | 0792373685 |
Internformat
MARC
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| 100 | 1 | |a Bening, Lionel |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Principles of verifiable RTL design |b a functional coding style supporting verification processes in Verilog |c Lionel Bening and Harry Foster |
| 250 | |a 2. ed., 3. printing | ||
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 2002 | |
| 300 | |a XXIII, 281 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references (p. [247]-254) and index | ||
| 650 | 4 | |a Register-Transfer-Ebene | |
| 650 | 4 | |a RTL (Computer program language) | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a Register-Transfer-Ebene |0 (DE-588)4215789-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Register-Transfer-Ebene |0 (DE-588)4215789-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Foster, Harry |e Sonstige |4 oth | |
Datensatz im Suchindex
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|---|---|
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| any_adam_object | |
| author | Bening, Lionel |
| author_facet | Bening, Lionel |
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| building | Verbundindex |
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| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
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| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 190 |
| ctrlnum | (OCoLC)248983019 (DE-599)BVBBV014418099 |
| dewey-full | 621.395 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-search | 621.395 621.39/5 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. ed., 3. printing |
| format | Book |
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| id | DE-604.BV014418099 |
| illustrated | Illustrated |
| indexdate | 2024-07-20T07:57:56Z |
| institution | BVB |
| isbn | 0792373685 |
| language | English |
| lccn | 2001029619 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012766052 |
| oclc_num | 248983019 |
| open_access_boolean | |
| owner | DE-703 |
| owner_facet | DE-703 |
| physical | XXIII, 281 S. graph. Darst. |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | Kluwer |
| record_format | marc |
| spelling | Bening, Lionel Verfasser aut Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster 2. ed., 3. printing Boston [u.a.] Kluwer 2002 XXIII, 281 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references (p. [247]-254) and index Register-Transfer-Ebene RTL (Computer program language) Verilog (Computer hardware description language) Register-Transfer-Ebene (DE-588)4215789-4 gnd rswk-swf Register-Transfer-Ebene (DE-588)4215789-4 s DE-604 Foster, Harry Sonstige oth |
| spellingShingle | Bening, Lionel Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Register-Transfer-Ebene RTL (Computer program language) Verilog (Computer hardware description language) Register-Transfer-Ebene (DE-588)4215789-4 gnd |
| subject_GND | (DE-588)4215789-4 |
| title | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog |
| title_auth | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog |
| title_exact_search | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog |
| title_full | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster |
| title_fullStr | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster |
| title_full_unstemmed | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster |
| title_short | Principles of verifiable RTL design |
| title_sort | principles of verifiable rtl design a functional coding style supporting verification processes in verilog |
| title_sub | a functional coding style supporting verification processes in Verilog |
| topic | Register-Transfer-Ebene RTL (Computer program language) Verilog (Computer hardware description language) Register-Transfer-Ebene (DE-588)4215789-4 gnd |
| topic_facet | Register-Transfer-Ebene RTL (Computer program language) Verilog (Computer hardware description language) |
| work_keys_str_mv | AT beninglionel principlesofverifiablertldesignafunctionalcodingstylesupportingverificationprocessesinverilog AT fosterharry principlesofverifiablertldesignafunctionalcodingstylesupportingverificationprocessesinverilog |