Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic Publishers
2002
|
| Ausgabe: | 2. ed. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XXIV, 328 S. graph. Darst. |
| ISBN: | 0792376447 |
Internformat
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| 100 | 1 | |a Bhatnagar, Himanshu |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Advanced ASIC chip synthesis |b using Synopsys Design Compiler, Physical Compiler, and PrimeTime |c Himanshu Bhatnagar |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a Boston |b Kluwer Academic Publishers |c 2002 | |
| 300 | |a XXIV, 328 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 7 | |a Circuits intégrés pour applications spécifiques - conception assistée par ordinateur |2 ram | |
| 650 | 7 | |a Compilateurs (logiciels) |2 ram | |
| 650 | 7 | |a Conception logique - traitement des données |2 ram | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Application specific integrated circuits |x Computer-aided design | |
| 650 | 4 | |a Compilers (Computer programs) | |
| 650 | 4 | |a Logic design |x Data processing | |
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| 650 | 0 | 7 | |a Chip |0 (DE-588)4197163-2 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
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|---|---|
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Contents
Foreword Xv
Preface xv//
Acknowledgements xxiii
About The Author xcv
CHAPTER 1: ASIC DESIGN METHODOLOGY 1
1.1 Traditional Design Flow 2
1.1.1 Specification and RTL Coding 4
1.1.2 Dynamic Simulation 5
1.1.3 Constraints, Synthesis and Scan Insertion 6
1.1.4 Formal Verification 8
1.1.5 Static Timing Analysis using PrimeTime 10
1.1.6 Placement, Routing and Verification 11
1.1.7 Engineering Change Order 12
1.2 Physical Compiler Flow 13
1.2.1 Physical Synthesis 16
1.3 Chapter Summary 17
viii
CHAPTER 2: TUTORIAL 19
2.1 Example Design 20
2.2 Initial Setup 21
2.3 Traditional Flow 22
2.3.1 Pre Layout Steps 22
2.3.2 Post Layout Steps 36
2.4 Physical Compiler Flow 42
2.5 Chapter Summary 42
CHAPTER 3: BASIC CONCEPTS 45
3.1 Synopsys Products 45
3.2 Synthesis Environment 48
3.2.1 Startup Files 48
3.2.2 System Library Variables 49
3.3 Objects, Variables and Attributes 51
3.3.1 Design Objects 51
3.3.2 Variables 52
3.3.3 Attributes 53
3.4 Finding Design Objects 54
3.5 Synopsys Formats 55
3.6 Data Organization 55
3.7 Design Entry 56
3.8 Compiler Directives 57
3.8.1 HDL Compiler Directives 58
3.8.2 VHDL Compiler Directives 60
3.9 Chapter Summary 61
CHAPTER 4: SYNOPSYS TECHNOLOGY LIBRARY 63
4.1 Technology Libraries 64
4.1.1 Logic Library 64
4.1.2 Physical Library 64
4.2 Logic Library Basics 65
4.2.1 Library Group 65
4.2.2 Library Level Attributes 66
4.2.3 Environment Description 66
4.2.4 Cell Description 71
4.3 Delay Calculation 74
4.3.1 Delay Model 74
Contents ix
4.3.2 Delay Calculation Problems 76
4.4 What is a Good Library? 77
4.5 Chapter Summary 79
CHAPTER 5: PARTITIONING AND CODING STYLES 81
5.1 Partitioning for Synthesis 82
5.2 What is RTL? 84
5.2.1 Software versus Hardware 84
5.3 General Guidelines 85
5.3.1 Technology Independence 85
5.3.2 Clock Related Logic 85
5.3.3 No Glue Logic at the Top 86
5.3.4 Module Name Same as File Name 86
5.3.5 Pads Separate from Core Logic 87
5.3.6 Minimize Unnecessary Hierarchy 87
5.3.7 Register All Outputs 87
5.3.8 Guidelines for FSM Synthesis 87
5.4 Logic Inference 88
5.4.1 Incomplete Sensitivity Lists 88
5.4.2 Memory Element Inference 89
5.4.3 Multiplexer Inference 94
5.4.4 Three State Inference 97
5.5 Order Dependency 98
5.5.1 Blocking versus Non Blocking Assignments in Verilog 98
5.5.2 Signals versus Variables in VHDL 99
5.6 Chapter Summary 100
CHAPTER 6: CONSTRAINING DESIGNS 101
6.1 Environment and Constraints 102
6.1.1 Design Environment 102
6.1.2 Design Constraints 107
6.2 Advanced Constraints 114
6.3 Clocking Issues 116
6.3.1 Pre Layout 117
6.3.2 Post Layout 118
6.3.3 Generated Clocks 119
6.4 Putting it Together 120
6.5 Chapter Summary 122
X
CHAPTER 7: OPTIMIZING DESIGNS 125
7.1 Design Space Exploration 125
7.2 Total Negative Slack 129
7.3 Compilation Strategies 131
7.3.1 Top Down Hierarchical Compile 131
7.3.2 Time Budgeting Compile 132
7.3.3 Compile Characterize Write Script Recompile 134
7.3.4 Design Budgeting 135
7.4 Resolving Multiple Instances 137
7.5 Optimization Techniques 139
7.5.1 Compiling the Design 139
7.5.2 Flattening and Structuring 141
7.5.3 Removing Hierarchy 144
7.5.4 Optimizing Clock Networks 145
7.5.5 Optimizing for Area 148
7.6 Chapter Summary 148
CHAPTER 8; DESIGN FOR TEST 151
8.1 Types of DFT 151
8.1.1 Memory and Logic BIST 152
8.1.2 Boundary Scan DFT 153
8.2 Scan Insertion 153
8.2.1 Shift and Capture Cycles 154
8.2.2 RTL Checking 157
8.2.3 Making Design Scannable 158
8.2.4 Existing Scan 161
8.2.5 Scan Chain Ordering 162
8.2.6 Test Pattern Generation 164
8.2.7 Putting it Together 165
8.3 DFT Guidelines 166
8.3.1 Tri State Bus Contention 167
8.3.2 Latches 167
8.3.3 Gated Reset or Preset 167
8.3.4 Gated or Generated Clocks 168
8.3.5 Use Single Edge of the Clock 169
Contents xi
8.3.6 Multiple Clock Domains 169
8.3.7 Order Scan Chains to Minimize Clock Skew 170
8.3.8 Logic Un Scannable due to Memory Element 170
8.4 Chapter Summary 173
CHAPTER 9; LINKS TO LAYOUT POST LAYOUT OPT. 175
9.1 Generating Netlist for Layout 177
9.1.1 Uniquify 177
9.1.2 Tailoring the Netlist for Layout 179
9.1.3 Remove Unconnected Ports 180
9.1.4 Visible Port Names 180
9.1.5 Verilog Specific Statements 181
9.1.6 Unintentional Clock or Reset Gating 182
9.1.7 Unresolved References 183
9.2 Layout 183
9.2.1 Floorplanning 183
9.2.2 Clock Tree Insertion 188
9.2.3 Transfer of Clock Tree to Design Compiler 192
9.2.4 Routing 194
9.2.5 Extraction 194
9.3 Post Layout Optimization 199
9.3.1 Back Annotation and Custom Wire Loads 200
9.3.2 In Place Optimization 202
9.3.3 Location Based Optimization 203
9.3.4 Fixing Hold Time Violations 205
9.4 Chapter Summary 209
CHAPTER 10: PHYSICAL SYNTHESIS 211
10.1 Initial Setup 212
10.1.1 Important Variables 212
10.2 Modes of Operation 213
10.2.1 RTL 2 Placed Gates 213
10.2.2 Gates to Placed Gates 216
10.3 Other PhyC Commands 220
10.4 Physical Compiler Issues. 221
10.5 Back End Flow 223
10.6 Chapter Summary 223
xii
CHAPTER 11: SDF GENERATION 225
11.1 SDF File 226
11.2 SDF File Generation 228
11.2.1 Generating Pre Layout SDF File 228
11.2.2 Generating Post Layout SDF File 231
11.2.3 Issues Related to Timing Checks 232
11.2.4 False Delay Calculation Problem 233
11.2.5 Putting it Together 235
11.3 Chapter Summary 237
CHAPTER 12: PRIMETEME BASICS 239
12.1 Introduction 240
12.1.1 Invoking PT 240
12.1.2 PrimeTime Environment 240
12.1.3 Automatic Command Conversion 241
12.2 Tel Basics 242
12.2.1 Command Substitution 243
12.2.2 Lists 243
12.2.3 Flow Control and Loops 245
12.3 PrimeTime Commands 245
12.3.1 Design Entry 245
12.3.2 Clock Specification 246
12.3.3 Timing Analysis Commands 250
12.3.4 Other Miscellaneous Commands 256
12.4 Chapter Summary 259
CHAPTER 13: STATIC TIMING ANALYSIS 261
13.1 Why Static Timing Analysis? 261
13.1.1 What to Analyze? 262
13.2 Timing Exceptions 263
13.2.1 Multicycle Paths 263
13.2.2 False Paths 267
13.3 Disabling Timing Arcs 270
13.3.1 Disabling Timing Arcs Individually 270
13.3.2 Case Analysis 272
13.4 Environment and Constraints 272
13.4.1 Operating Conditions A Dilemma 273
13.5 Pre Layout 274
Contents xiii
13.5.1 Pre Layout Clock Specification 275
13.5.2 Timing Analysis 276
13.6 Post Layout 278
13.6.1 What to Back Annotate? 278
13.6.2 Post Layout Clock Specification 279
13.6.3 Timing Analysis 280
13.7 Analyzing Reports 284
13.7.1 Pre Layout Setup Time Analysis Report 285
13.7.2 Pre Layout Hold Time Analysis Report 286
13.7.3 Post Layout Setup Time Analysis Report 289
13.7.4 Post Layout Hold Time Analysis Report 291
13.8 Advanced Analysis 292
13.8.1 Detailed Timing Report 293
13.8.2 Cell Swapping 296
13.8.3 Bottleneck Analysis 297
13.8.4 Clock Gating Checks 300
13.9 Chapter Summary 303
APPENDIX A 306
APPENDIX B 319
INDEX 321 |
| any_adam_object | 1 |
| author | Bhatnagar, Himanshu |
| author_facet | Bhatnagar, Himanshu |
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| author_sort | Bhatnagar, Himanshu |
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| ctrlnum | (OCoLC)248634669 (DE-599)BVBBV014385664 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. ed. |
| format | Book |
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| indexdate | 2024-09-06T00:13:27Z |
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| language | English |
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| spelling | Bhatnagar, Himanshu Verfasser aut Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime Himanshu Bhatnagar 2. ed. Boston Kluwer Academic Publishers 2002 XXIV, 328 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Circuits intégrés pour applications spécifiques - conception assistée par ordinateur ram Compilateurs (logiciels) ram Conception logique - traitement des données ram Datenverarbeitung Application specific integrated circuits Computer-aided design Compilers (Computer programs) Logic design Data processing Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Chip (DE-588)4197163-2 gnd rswk-swf Chip (DE-588)4197163-2 s Logischer Entwurf (DE-588)4168051-0 s Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009848203&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Bhatnagar, Himanshu Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime Circuits intégrés pour applications spécifiques - conception assistée par ordinateur ram Compilateurs (logiciels) ram Conception logique - traitement des données ram Datenverarbeitung Application specific integrated circuits Computer-aided design Compilers (Computer programs) Logic design Data processing Kundenspezifische Schaltung (DE-588)4122250-7 gnd Logischer Entwurf (DE-588)4168051-0 gnd Chip (DE-588)4197163-2 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4168051-0 (DE-588)4197163-2 |
| title | Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime |
| title_auth | Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime |
| title_exact_search | Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime |
| title_full | Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime Himanshu Bhatnagar |
| title_fullStr | Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime Himanshu Bhatnagar |
| title_full_unstemmed | Advanced ASIC chip synthesis using Synopsys Design Compiler, Physical Compiler, and PrimeTime Himanshu Bhatnagar |
| title_short | Advanced ASIC chip synthesis |
| title_sort | advanced asic chip synthesis using synopsys design compiler physical compiler and primetime |
| title_sub | using Synopsys Design Compiler, Physical Compiler, and PrimeTime |
| topic | Circuits intégrés pour applications spécifiques - conception assistée par ordinateur ram Compilateurs (logiciels) ram Conception logique - traitement des données ram Datenverarbeitung Application specific integrated circuits Computer-aided design Compilers (Computer programs) Logic design Data processing Kundenspezifische Schaltung (DE-588)4122250-7 gnd Logischer Entwurf (DE-588)4168051-0 gnd Chip (DE-588)4197163-2 gnd |
| topic_facet | Circuits intégrés pour applications spécifiques - conception assistée par ordinateur Compilateurs (logiciels) Conception logique - traitement des données Datenverarbeitung Application specific integrated circuits Computer-aided design Compilers (Computer programs) Logic design Data processing Kundenspezifische Schaltung Logischer Entwurf Chip |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009848203&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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