Asynchronous system on chip interconnect:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
London [u.a.]
Springer
2002
|
| Schriftenreihe: | Distinguished dissertations
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Zugl.: Manchester, Univ., Diss. |
| Beschreibung: | XVI, 138 S. graph. Darst. : 24 cm |
| ISBN: | 185233598X |
Internformat
MARC
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| 100 | 1 | |a Bainbridge, John |d 1582-1643 |e Verfasser |0 (DE-588)129551120 |4 aut | |
| 245 | 1 | 0 | |a Asynchronous system on chip interconnect |c John Bainbridge |
| 246 | 1 | 3 | |a Asynchronous system-on-chip interconnect |
| 264 | 1 | |a London [u.a.] |b Springer |c 2002 | |
| 300 | |a XVI, 138 S. |b graph. Darst. : 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Distinguished dissertations | |
| 500 | |a Zugl.: Manchester, Univ., Diss. | ||
| 650 | 4 | |a Asynchronous circuits | |
| 650 | 4 | |a Electronic digital computers |x Circuits |x Design and construction | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration | |
| 650 | 4 | |a Microcomputers |x Buses | |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Token-Bus |0 (DE-588)4322716-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Asynchrones Schaltwerk |0 (DE-588)4271581-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mikroprozessor |0 (DE-588)4039232-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Bus |g Informatik |0 (DE-588)4122982-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Asynchrone Übertragung |0 (DE-588)4225929-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | 1 | |a Asynchrones Schaltwerk |0 (DE-588)4271581-7 |D s |
| 689 | 0 | 2 | |a Token-Bus |0 (DE-588)4322716-8 |D s |
| 689 | 0 | 3 | |a Mikroprozessor |0 (DE-588)4039232-6 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Bus |g Informatik |0 (DE-588)4122982-4 |D s |
| 689 | 1 | 1 | |a Asynchrone Übertragung |0 (DE-588)4225929-0 |D s |
| 689 | 1 | |5 DE-604 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009800363&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009800363 | |
Datensatz im Suchindex
| _version_ | 1808136539459289088 |
|---|---|
| adam_text |
CONTENTS
1.
INTRODUCTION
.
1
1.1
ASYNCHRONOUS
DESIGN
AND
ITS ADVANTAGES
.
2
1.1.1
AVOIDANCE
OF
CLOCK-SKEW
.
2
1.1.2
LOW
POWER
.
2
1.1.3
IMPROVED
ELECTRO-MAGNETIC
COMPATIBILITY
(EMC)
.
3
1.1.4
MODULARITY
.
3
1.1.5
BETTER
THAN
WORST-CASE
PERFORMANCE
.
4
1.2
DISADVANTAGES
OF
ASYNCHRONOUS
DESIGN
.
4
1.2.1
COMPLEXITY
.
4
1.2.2
DEADLOCK
.
4
1.2.3
VERIFICATION
.
5
1.2.4
TESTABILITY
.
5
1.2.5
"
IT
'
S
NOT
SYNCHRONOUS
"
.
5
1.3
BOOK
OVERVIEW
.
5
1.4
PUBLICATIONS
.
7
2.
ASYNCHRONOUS
DESIGN
.
9
2.1
INTRODUCTION
.
9
2.2
ASYNCHRONOUS
DESIGN
.
10
2.2.1
CIRCUIT
CLASSIFICATION
.
11
2.2.2
THE
CHANNEL
.
11
2.2.3
SIGNALLING
CONVENTIONS
.
12
2.2.4
DATA
REPRESENTATION
.
13
2.2.5
THE
MULLER
C-ELEMENT
.
15
2.2.6
SPECIFICATIONS
AND
AUTOMATED
CIRCUIT
SYNTHESIS
.
16
2.2.7
METASTABILITY,
ARBITRATION
AND
SYNCHRONISATION
.
17
2.2.8
SUTHERLAND
'
S
MICROPIPELINES
.
18
2.2.9
LARGE
ASYNCHRONOUS
CIRCUITS
.
20
2.3
SUMMARY
.
21
3.
SYSTEM
LEVEL
INTERCONNECT
PRINCIPLES
_._
23
3.1
POINT-TO-POINT
COMMUNICATION
PATHS
.
23
3.2
MULTIPOINT
INTERCONNECT
TOPOLOGY
.
23
3.2.1
SHARED
BUSES
.
23
3.2.2
STAR
AND
RING
NETWORKS
.
24
3.2.3
MESHES
.
24
3.3
BUS
PROTOCOL
ISSUES
.
24
3.3.1
SERIAL
OPERATION
.
24
3.3.2
MULTIPLEXED
ADDRESS/DATA
LINES
.
25
3.3.3
SEPARATE
ADDRESS
AND
DATA
LINES
.
25
3.3.4
ARBITRATION
.
26
X
CONTENTS
3.3.5
ATOMIC
SEQUENCES
.
26
3.3.6
BURSTS
.
27
3.3.7
INTERLOCKED
OR
DECOUPLED
TRANSFERS
.
27
3.3.8
SPLIT
TRANSACTIONS
.
27
3.4
INTERCONNECT
PERFORMANCE
OBJECTIVES
.
27
3.5
COMMERCIAL
ON-CHIP
BUSES
.
28
3.5.1
PERIPHERAL
INTERCONNECT
BUS
(PL-BUS)
.
28
3.5.2
ADVANCED
MICROCONTROLLER
BUS
ARCHITECTURE
(AMBA)
.
28
3.5.3
CORECONNECT
.
29
3.6
SUMMARY
.
30
4.
THE
PHYSICAL
(WIRE)
LAYER
.
_
.
_
.
31
4.1
WIRE
THEORY
.
31
4.2
ELECTRICAL
AND
PHYSICAL
CHARACTERISTICS
.
32
4.3
TERMINATION
.
33
4.4
CROSSTALK
.
33
4.4.1
PROPAGATION
DELAY
FOR
WELL
SEPARATED
WIRES
.
35
4.4.2
SIGNAL
PROPAGATION
DELAY
WITH
CLOSE-PACKED
WIRES
.
36
4.4.3
ALTERNATIVE
WIRING
ARRANGEMENTS
.
36
4.5
SUMMARY
.
40
5.
THE
LINK
LAYER
.
41
5.1
CENTRALISED
VS
DISTRIBUTED
INTERFACES
.
41
5.2
SIGNALLING
CONVENTION
.
42
5.3
DATA
ENCODING
.
43
5.4
HANDSHAKE
SOURCES
.
43
5.5
BIDIRECTIONAL
DATA
TRANSFER
.
44
5.6
MULTIPLE
INITIATORS
ON
ONE
CHANNEL
.
45
5.6.1
ARBITRATION
.
45
5.6.2
REQUEST
DRIVE
AND
HAND-OVER
.
50
5.6.3
PUSH
DATA
DRIVE
AND
HAND-OVER
.
50
5.6.4
TRANSFER
DEFERRAL/HARDWARE
RETRY
.
51
5.6.5
ATOMIC
TRANSFERS
AND
LOCKING
.
52
5.7
MULTIPLE
TARGETS
.
54
5.7.1
ACKNOWLEDGE
DRIVE
AND
HAND-OVER
.
54
5.7.2
TARGET
SELECTION
.
55
5.7.3
DECODE
AND
TARGET
EXCEPTIONS
.
55
5.7.4
PULL
DATA
DRIVE
AND
HAND-OVER
.
56
5.7.5
DEFER
.
56
5.8
MULTIPOINT
BUS-CHANNEL
INTERFACES
.
56
5.9
MARBLE
'
S
LINK
LAYER
CHANNELS
.
58
5.10
SUMMARY
.
59
6.
PROTOCOL
LAYER
_
.
_
._
.
_
.
.
61
6.1
TRANSFER
PHASES
.
61
6.1.1
COMMAND
PHASE
.
62
6.1.2
ACKNOWLEDGE
PHASE
.
62
CONTENTS
XI
6.1.3
DATA
PHASE
.
62
6.1.4
RESPONSE
PHASE
.
63
6.2
EXCEPTIONS
.
63
6.3
DEFER
AND
BRIDGING
.
63
6.4
MAPPING
TRANSFER
PHASES
ONTO
CHANNEL
CYCLES
.
64
6.4.1
SEQUENTIAL
OPERATION
USING
A
SINGLE
CHANNEL
.
65
6.4.2
PARALLEL
OPERATION
USING
MULTIPLE
CHANNELS
.
66
6.5
TRANSFER
CYCLE
ROUTING
.
66
6.5.1
INTERLOCKED
PROTOCOLS
.
67
6.5.2
DECOUPLED
PROTOCOLS
.
68
6.6
TRANSFER
CYCLE
INITIATION
.
69
6.7
MARBLE
'
S
DUAL-CHANNEL
BUS
ARCHITECTURE
.
70
7.
TRANSACTION
LAYER
.
71
7.1
SPLIT
TRANSACTIONS
.
72
7.1.1
SPLIT
TRANSACTIONS
GIVE
BETTER
BUS
AVAILABILITY
.
72
7.1.2
IMPLEMENTATION
ON
AN
INTERLOCKED
PROTOCOL
LAYER
.
72
7.1.3
IMPLEMENTATION
ON
A
DECOUPLED
PROTOCOL-LAYER
.
74
7.2
RESPONSE
ORDERING
.
74
7.2.1
SINGLE
OUTSTANDING
COMMAND
.
76
7.2.2
MULTIPLE
OUTSTANDING
COMMANDS
AND
PIPELINING
.
77
7.2.3
NUMBER
OF
OUTSTANDING
COMMANDS
.
78
7.2.4
A
GROUPING
OF
SINGLE
OUTSTANDING
COMMAND
INTERFACES
.
78
7.2.5
SEQUENCE
TAGGING
AND
REORDERING
OF
RESPONSES
.
79
7.3
MARBLE
'
S
TRANSACTION
LAYER
.
81
8.
MARBLE:
A
DUAL-CHANNEL
SPLIT
TRANSFER
BUS
.83
8.1
MARBLE
PROTOCOL
AND
SIGNAL
SUMMARY
.
83
8.1.1
TWO
CHANNELS
.
83
8.1.2
SPLIT
TRANSACTIONS
.
85
8.1.3
EXCEPTIONS
.
86
8.1.4
ARBITRATION
.
86
8.1.5
ATOMIC
TRANSACTIONS
AND
LOCKING
.
86
8.1.6
BURST
OPTIMISATION
.
86
8.2
BUS
TRANSACTION
INTERFACE
IMPLEMENTATION
.
87
8.2.1
INTERFACE
STRUCTURE
.
88
8.2.2
DATA
STORAGE
AND
MANIPULATION
.
88
8.2.3
TOKEN
MANAGEMENT
.
91
8.3
MARBLE
IN
THE
AMULET3H
SYSTEM
.
91
8.3.1
AMULET3
PROCESSOR
CORE
.
92
8.3.2
RAM
.
94
8.3.3
ROM
.
94
8.3.4
DMA
CONTROLLER
.
95
8.3.5
EXTERNAL
MEMORY/TEST
INTERFACE
.
95
8.3.6
ADC/AEDL
.
95
8.3.7
SOCB
.
95
XII
CONTENTS
8.3.8
INSTRUCTION
BRIDGE
AND
LOCAL
BUS
.
97
8.3.9
DATA
BRIDGE
AND
LOCAL
BUS
.
98
8.4
SUMMARY
.
99
9.
EVALUATION
.
101
9.1
MARBLE
TESTBED
.
101
9.2
SIMULATION
OF
MARBLE
IN
AMULET3H
.
102
9.2.1
SINGLE
INITIATOR
TO
SINGLE
TARGET
.
103
9.2.2
TWO
INITIATORS
ACCESSING
DIFFERENT
TARGETS
.
104
9.2.3
TWO
INITIATORS
ACCESSING
THE
SAME
TARGET
.
105
9.2.4
THREE
INITIATORS
ACCESSING
DIFFERENT
TARGETS
.
106
9.3
ANALYSIS
OF
DELAY
DISTRIBUTION
.
107
9.3.1
CENTRALISED
AND
DISTRIBUTED
DECODING
.
109
9.3.2
ARBITRATION
.
109
9.3.3
DATA
DRIVE
SETUP
TIME
.
110
9.3.4
PIPELINE
LATCH
CONTROLLER
DELAYS
.
ILL
9.3.5
SENDER
ACTIVITY
.
ILL
9.3.6
PERFORMANCE
SUMMARY
.
112
9.4
HARDWARE
REQUIREMENTS
.
112
9.5
COMPARISON
WITH
SYNCHRONOUS
ALTERNATIVES
.
113
10.
CONCLUSION
.
115
10.1
ADVANTAGES
AND
DISADVANTAGES
OF
MARBLE
.
115
10.1.1
INCREASED
MODULARITY
.
115
10.1.2
AVOIDANCE
OF
CLOCK-SKEW
.
116
10.1.3
LOW
POWER
CONSUMPTION
.
116
10.1.4
IMPROVED
ELECTRO-MAGNETIC
COMPATIBILITY
(EMC)
.
117
10.1.5
PERFORMANCE
.
117
10.1.6
RISK
OF
DEADLOCK
.
117
10.1.7
TIMING
VERIFICATION
.
117
10.1.8
DESIGN
COMPLEXITY
.
118
10.1.9
RELIABLE
ARBITRATION
.
118
10.2
IMPROVING
THE
MARBLE
BUS
.
119
10.2.1
SEPARATING
THE
READ-AND
WRITE-DATA
PATHS
.
119
10.2.2
LESS
CONSERVATIVE
DRIVE
OVERLAP
PREVENTION
.
119
10.2.3
ALLOWING
MULTIPLE
OUTSTANDING
COMMANDS
.
119
10.3
ALTERNATIVE
INTERCONNECT
SOLUTIONS
AND
FUTURE
WORK
.
120
10.3.1
CHANGING
THE
INTERCONNECT
TOPOLOGY
.
120
10.3.2
CHANGING
TO
A
DELAY-INSENSITIVE
DATA
ENCODING
.
121
10.4
THE
FUTURE
OF
ASYNCHRONOUS
SOC
INTERCONNECT?
.
122
APPENDIX
A:
MARBLE
SCHEMATICS
.
123
AL
BUS
INTERFACE
TOP
LEVEL
SCHEMATICS
.
123
A2
INITIATOR
INTERFACE
CONTROLLERS
.
123
A3
TARGET
INTERFACE
CONTROLLERS
.
124
A4
BUS
DRIVERS
AND
BUFFERS
.
127
A5
LATCH
CONTROLLERS
.
128
CONTENTS XIII
A6
CENTRALISED
BUS
CONTROL
UNITS
.
128
REFERENCES
.
133
INDEX
.
139 |
| any_adam_object | 1 |
| author | Bainbridge, John 1582-1643 |
| author_GND | (DE-588)129551120 |
| author_facet | Bainbridge, John 1582-1643 |
| author_role | aut |
| author_sort | Bainbridge, John 1582-1643 |
| author_variant | j b jb |
| building | Verbundindex |
| bvnumber | BV014289157 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.B87 |
| callnumber-search | TK7895.B87 |
| callnumber-sort | TK 47895 B87 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)49238588 (DE-599)BVBBV014289157 |
| dewey-full | 621.3981 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3981 |
| dewey-search | 621.3981 |
| dewey-sort | 3621.3981 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV014289157 |
| illustrated | Illustrated |
| indexdate | 2024-08-23T00:36:16Z |
| institution | BVB |
| isbn | 185233598X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009800363 |
| oclc_num | 49238588 |
| open_access_boolean | |
| owner | DE-29T |
| owner_facet | DE-29T |
| physical | XVI, 138 S. graph. Darst. : 24 cm |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | Springer |
| record_format | marc |
| series2 | Distinguished dissertations |
| spelling | Bainbridge, John 1582-1643 Verfasser (DE-588)129551120 aut Asynchronous system on chip interconnect John Bainbridge Asynchronous system-on-chip interconnect London [u.a.] Springer 2002 XVI, 138 S. graph. Darst. : 24 cm txt rdacontent n rdamedia nc rdacarrier Distinguished dissertations Zugl.: Manchester, Univ., Diss. Asynchronous circuits Electronic digital computers Circuits Design and construction Integrated circuits Very large scale integration Microcomputers Buses Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Token-Bus (DE-588)4322716-8 gnd rswk-swf Asynchrones Schaltwerk (DE-588)4271581-7 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Bus Informatik (DE-588)4122982-4 gnd rswk-swf Asynchrone Übertragung (DE-588)4225929-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Schaltungsentwurf (DE-588)4179389-4 s Asynchrones Schaltwerk (DE-588)4271581-7 s Token-Bus (DE-588)4322716-8 s Mikroprozessor (DE-588)4039232-6 s DE-604 Bus Informatik (DE-588)4122982-4 s Asynchrone Übertragung (DE-588)4225929-0 s DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009800363&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Bainbridge, John 1582-1643 Asynchronous system on chip interconnect Asynchronous circuits Electronic digital computers Circuits Design and construction Integrated circuits Very large scale integration Microcomputers Buses Schaltungsentwurf (DE-588)4179389-4 gnd Token-Bus (DE-588)4322716-8 gnd Asynchrones Schaltwerk (DE-588)4271581-7 gnd Mikroprozessor (DE-588)4039232-6 gnd Bus Informatik (DE-588)4122982-4 gnd Asynchrone Übertragung (DE-588)4225929-0 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4322716-8 (DE-588)4271581-7 (DE-588)4039232-6 (DE-588)4122982-4 (DE-588)4225929-0 (DE-588)4113937-9 |
| title | Asynchronous system on chip interconnect |
| title_alt | Asynchronous system-on-chip interconnect |
| title_auth | Asynchronous system on chip interconnect |
| title_exact_search | Asynchronous system on chip interconnect |
| title_full | Asynchronous system on chip interconnect John Bainbridge |
| title_fullStr | Asynchronous system on chip interconnect John Bainbridge |
| title_full_unstemmed | Asynchronous system on chip interconnect John Bainbridge |
| title_short | Asynchronous system on chip interconnect |
| title_sort | asynchronous system on chip interconnect |
| topic | Asynchronous circuits Electronic digital computers Circuits Design and construction Integrated circuits Very large scale integration Microcomputers Buses Schaltungsentwurf (DE-588)4179389-4 gnd Token-Bus (DE-588)4322716-8 gnd Asynchrones Schaltwerk (DE-588)4271581-7 gnd Mikroprozessor (DE-588)4039232-6 gnd Bus Informatik (DE-588)4122982-4 gnd Asynchrone Übertragung (DE-588)4225929-0 gnd |
| topic_facet | Asynchronous circuits Electronic digital computers Circuits Design and construction Integrated circuits Very large scale integration Microcomputers Buses Schaltungsentwurf Token-Bus Asynchrones Schaltwerk Mikroprozessor Bus Informatik Asynchrone Übertragung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009800363&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT bainbridgejohn asynchronoussystemonchipinterconnect |