FPGA 2002: Monterey, California, USA February 24 - 26, 2002
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
ACM Press
2002
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 258 S. Illl., graph. Darst. |
| ISBN: | 1581134525 |
Internformat
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Datensatz im Suchindex
| _version_ | 1804129047678025728 |
|---|---|
| adam_text | Table
of
Contents
Session
1.
Interconnect
Architecture
Chair: S.
Wilton. University of British Columbia
Interconnect Enhancements for a High-Speed
PLD
Architecture
...........................................................3
M
Hutton,
V. Chan. P. Kazarian. V.
Maniri.
T.
Ngai.
J.
Park.
R.
Patel.
B. Pederscn.
J. Schleichcr. S. Shumarayev,
Altera
FPGA
Switch Block Layout and Evaluation
................................................................................................11
H. Schmit,
V. Chandra. Carnegie Mellon University
Circuit Design of Routing Switches
.............................................................................................................19
G. Lemieux, D. Lewis, University of Toronto
Session
2.
Arithmetic
Chair: T. Kean. Algotronix
A Faster Distributed Arithmetic Architecture for FPGAs
..........................................................................31
R. S.
Grover,
W.
Shang,
Q.
Li. Santa Clara
Universito
Efficient Architectures for Implementing Montgomery Modular Multiplication and RSA
Modular Exponentiation on
Reconfigurable
Logic
....................................................................................40
A. Daly, W.
Marnane.
University College Cork
A Flexible
Floating-Point
Format for Optimizing Data-Paths and Operators
in FPGA Based DSPs
.....................................................................................................................................50
J. Dido.
N.
Geraudie. L. Loiseau. O.
Payeur. Y.
Savaria,
Ecole Polytechnique
cle
Montréal;
D.
Poirier,
Miranda
Technologies, ¡ne.
Session
3.
Physical
Design
Chair: R. Tessier.
University of
Massachusetts
-
Amherst
Efficient Circuit
Clustering for Area and
Power
Reduction in
FPGAs
....................................................59
A.
Singh,
M. Marek-Sadowska.
University of California,
Santa Barbara
Integrated Retiming and Placement for Field Programmable Gate Arrays
............................................67
D. P. Singh.
S. D.
Brown, University of Toronto
SPFD-Based Global Rewiring
.......................................................................................................................77
J. Cong. Y. Lin. V. Long, University of California, Los Angeles
Eve: A CAD Tool for Manual Placement and Pipelining Assistance of FPGA Circuits
........................85
W. Chow. J. Rose. University of Toronto
Session
4.
Cellular and Cryptographic Applications
Chair: S. Hauck. University of Washington
Application of FPGA Technology to Accelerate the Finite-Difference Time-Domain
(FDTD) Method
.................................................................................................................................................97
R.
N.
Schneider.
L
E.
Turner.
M M.
Okomewski. University ofCalgoiy
FPGA Implementation of Neighborhood-of-Four Cellular Automata Random Number Generators
106
В
Shackleford. M.Tanaka. R. J. Carter. G. Snider. Hewlett-Packard
Cryptographic Rights Management of FPGA Intellectual Property Cores
113
T. Kean, Algotronix Ltd.
Session 5.
Synthesis, Verification and Test
Chair: J. Cong, UCLA
Constrained Clock Shifting for Field Programmable Gate Arrays
..........................................................121
D. P. Singh, S. D. Brown, University of Toronto
Timing Verification of Dynamically
Reconfigurable
Logic for the Xilinx
Virtex FPGA
Series
127
I. Robertson, J. Irvine, P. Lysaght, University of Strathclyde; D. Robinson, The Alba Center
FPGA Test Time Reduction Through a Novel Interconnect Testing Scheme
........................................136
S. McCracken, Z. Zelic, McGill University
Session
6,
Architecture Analysis and Automation
Chair: V. Betz,
Altera
On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions,
Tools and Techniques
....................................................................................................................................147
A. Yan, R. Cheng, S. Wilton, University of British Columbia
Dynamic Power Consumption in Virtex™-ll FPGA Family
.......................................................................157
L. Shang, Princeton University; A. S. Kaviani, K. Bathala, Xilinx, Inc.
Automatic Layout of Domain-Specific
Reconfigurable
Subsystems for System-on-a-Chip
...............165
S. Phillips, S. Hauck, University of Washington
Session
7.
Software for
Reconfigurable
Systems
Chair: M. Leeser. Sortheastern University
Performance-Constrained Pipelining of Software Loops onto
Reconfigurable
Hardware
..................177
G. Snider. Hewlett-Packard
Configuration Prefetching Techniques for Partial
Reconfigurable
Coprocessor
with Relocation and
Defragmentation
.........................................................................................................187
Z.
Li. Sorthw
estem
University:
S.
Hauck. University of Washington
Analysis of Quasi-Static Scheduling Techniques in a Virtualized
Reconfigurable
Machine
...............196
Y. Ylarkovskiy.
E. Caspi.
R.
Huang. J. Yeh,
M. Chu.
J. Wawrzynek, University of California, Berkeley;
A. DeHon.
California
Institute of Technonogy
Incremental Reconfiguration of Multi-FPGA Systems
..............................................................................206
K.K. Lee. Synopsvs: D.F. Wong.
Universit)
of Texas at Austin
Session
8.
Innovative Applications
Chair: R. Andraka. Andraka Consulting Group
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging
................217
S. Cork. M. Leeser. E. Miller. Northeastern University, M.
Trepanier,
Mercury Computer Systems
A Dynamically
Reconfigurable
Adaptive Viterbi Decoder
........................................................................227
S. Swaminathan. R. Tessier. D. Goeckel. W. Burleson, University of Massachusetts, Amherst
Data Reorganization Engines for the Next Generation of System-On-a-Chip FPGAs
..........................237
P.
Dini/.
J. Park.
University
of Southern Califomia/ISI
Posters
Prototyping Methodology for FPGA Architecture
......................................................................................247
M.
Akii,
R. Vodišck, A.
Žemva
Reconfigurable Computing
for Floating
Point Intensive
Iterative
Applications
....................................247
B.
Bishop,
T. P. Kellihcr
IP Based Synthesis of
Reconfigurables
Systems
......................................................................................248
C.
Bobda
FFiSim: A Simulation-Based Fault Injection Tool for Self-Stabilization Testing
of FPGA Designs
.............................................................................................................................................248
M.
Böhnel. R.
Weiss
Pattern Selection in Programmable Systems
.............................................................................................249
E. Bozorgzadeh, R.
Kastner.
S.
Ogrenci Memik, M. Sarrafzadeh
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA Using
an
Iso-Area
Approach
....................................................................................................................................249
V. Chandra, H. Schmit
The SmartDIMM Platform as
a Reconfigurable System-on-Chip
Prototype
..........................................249
L. Coraor, P. Hulina, L. Roth
Liquid Logic Extension (LLX) Technology
..................................................................................................250
M
Ferranti
Harnessing FPGAs for Computer Architecture Education
.......................................................................250
M. Holland, J. Harris, S. Hauck
Dynamic Hardware
Plugins
(DHPs) in an FPGA with Partial Run-time Reconfiguration (RTR)
..........250
E. L.
Horta,
J.
W.
Lockwood,
D.
E. Taylor,
D.
Parlour
Rapid Routability Estimation for FPGAs
.....................................................................................................251
P.
Kannan,
S. Balachandran. D. Bhatia
BEE: A Large-Scale FPGA-Based Emulation Engine
................................................................................251
K. Kuusilinna, C. Chang. R. Brodersen. G. Wright
Checkboard
Switch Block Topologies for Routing Diversity
...................................................................252
G. Lemieux, D. Lewis
FPGA Implementation of a Serially Organized DA Multichannel FIR Filter
............................................252
J. Leon, M.
Melgarejo
Dynamically
Reconfigurable
Intellectual Property (DRIP) Cores
............................................................252
J. MacBeth. P. Lysaght. I. Robertson
Floating-Point-Like Arithmetic for FPGA
.....................................................................................................253
R.
Matoušek.
M.
Ličko.
A. Heřmánek.
С.
Softley
Scheduling a Chain of Coarse-Grained Tasks on an Array of
Reconfigurable
FPGAs
253
D. P. Mehta.
С
Shetters. D. W. Bouldin
An FPGA Implementation of Triangle Mesh Decompression
..................................................................254
T. Mitra. T.
Chiueh
CAD Tool for Automatic
Latency-Optimal Implementation of FPGA-Based Systolic Arrays
..............254
J. G. Nash
An Efficient FPGA Implementation of the SPIHT Algorithm
.....................................................................255
J.
Ritter.
Ci.
Fey. P.
Molitor
Timing Configuration Switch in
Reconfigurable
Functional Cache Based Architectures
...................255
R. Sangireddy. H. Kim, A. K. Somani
High Quality Deterministic Timing Driven FPGA Placement
....................................................................256
VI. Senn. U.
Seidl.
F.
Johannes
Board-Level Net Assignment via Satisfiability
...........................................................................................256
X. Song. W. Hung. A. Mishehenko. M. Chrzanowska-Jeske, A. Coppola, A. Kennings
A FPGA Based MPEG-4 Video Encoder
......................................................................................................256
Author Index
.....................................................................................................................................................257
|
| any_adam_object | 1 |
| author_corporate | FPGA Monterey, Calif |
| author_corporate_role | aut |
| author_facet | FPGA Monterey, Calif |
| author_sort | FPGA Monterey, Calif |
| building | Verbundindex |
| bvnumber | BV014169050 |
| classification_rvk | SS 2002 |
| classification_tum | ELT 552f |
| ctrlnum | (OCoLC)634496685 (DE-599)BVBBV014169050 |
| discipline | Informatik Elektrotechnik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 2002 Monterey Calif. |
| id | DE-604.BV014169050 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:58:56Z |
| institution | BVB |
| institution_GND | (DE-588)1248125-7 (DE-588)10620-3 |
| isbn | 1581134525 |
| language | English |
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| physical | VIII, 258 S. Illl., graph. Darst. |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | ACM Press |
| record_format | marc |
| spelling | FPGA 10 2002 Monterey, Calif. Verfasser (DE-588)1248125-7 aut FPGA 2002 Monterey, California, USA February 24 - 26, 2002 tenth ACM International Symposium on Field-Programmable Gate Arrays FPGA '02 New York, NY ACM Press 2002 VIII, 258 S. Illl., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Field programmable gate array (DE-588)4347749-5 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2002 Monterey Calif. gnd-content Field programmable gate array (DE-588)4347749-5 s DE-604 Association for Computing Machinery Special Interest Group on Design Automation Sonstige (DE-588)10620-3 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009712879&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)1071861417 |
| title | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 |
| title_alt | FPGA '02 |
| title_auth | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 |
| title_exact_search | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 |
| title_full | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 tenth ACM International Symposium on Field-Programmable Gate Arrays |
| title_fullStr | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 tenth ACM International Symposium on Field-Programmable Gate Arrays |
| title_full_unstemmed | FPGA 2002 Monterey, California, USA February 24 - 26, 2002 tenth ACM International Symposium on Field-Programmable Gate Arrays |
| title_short | FPGA 2002 |
| title_sort | fpga 2002 monterey california usa february 24 26 2002 |
| title_sub | Monterey, California, USA February 24 - 26, 2002 |
| topic | Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Field programmable gate array Konferenzschrift 2002 Monterey Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009712879&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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