ICCAD 2001: November 4 - 8, 2001, Doubletree Hotel, San Jose, CA
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
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2001
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXV, 656 S. Ill., graph. Darst. |
| ISBN: | 0780372476 0780372484 |
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| 111 | 2 | |a International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) |d 2001 |c San José, Calif. |j Verfasser |0 (DE-588)10038981-8 |4 aut | |
| 245 | 1 | 0 | |a ICCAD 2001 |b November 4 - 8, 2001, Doubletree Hotel, San Jose, CA |c IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 |
| 246 | 1 | 3 | |a IEEE ACM digest of technical papers |
| 246 | 1 | 3 | |a Proceeding of the 2001 International Conference on Computer-Aided Design |
| 264 | 1 | |a Piscatay, NJ |b IEEE [u.a.] |c 2001 | |
| 300 | |a XXV, 656 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 2001 |z San Jose Calif. |2 gnd-content | |
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Datensatz im Suchindex
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Table
of Contents
Foreword
.
iii
Conference Committee
.xvi
Technical Program Committee
.xvii
Reviewers
.xiv
Keynote
.xxii
Tutorial
1:
Electrical-Integrity Design and Verification for
* * xxiii
Digital and Mixed-Signal Systems-On-A-Chip
Tutorial
2:
Boolean Satisfiability Solving and Its Application
* xxiv
in Equivalence and Model Checking
Tutorial
3:
Optimization Strategies for Physical
.xxv
Synthesis and Timing Closure
Session 1A: Dynamic Verification
Moderators: Jay Lawrence, Cadence Design Systems, Inc., Chelmsford, MA
Kunle Olokotun, Stanford University, Stanford, CA
1A.1 Static Scheduling of Multi-Domain Memories for Functional Verification.
. 2
Murali.
Kudlugi, Charles Selvidge, Russell Tessier
ÍAJ.
A Simulation-Based Method for the Verification of Shared Memory
.10
hi Multiprocessor Systems
Scott Taylor, CarlRamey, Craig Barrier, David Asher
1A.3 Predicting the Performance of Synchronous Discrete Event Simulation
.18
Systems
Jinsheng Xu, Moon Jung Chung
Session IB: System-Level Exploration and Design
Moderatars:
Ύ
anhing
Li, Synopsys, Inc., Mountain View, CA
Xiaobo (Sharon)
Ни,
University of Notre Dame, Notre Dame, IN
1B.1 System-Level Exploration for Pareto-Optimal Configurations
.25
hi Parameterized Systems-on-a-Chip
Tony Givargis, Frank Wahid,
Jörg Henkel
1В.2
System
Level
Design
with SPADE: An
M-JPEG
Case Study
.31
Paul Lieverse, Todor
Štefanov,
Pieter
van
der Wolf,
Ed Deprettere
1B.3 NetBench:
A Benchmarking
Suite
for
Network
Processors.
39
Gokhan
Mentik,
William
H.
Mangione-Smith, Wendong Hu
Session 1С:
Interconnect Planning
Moderators:
Robi
Butta,
Synopsys, Inc., Mountain View, CA
Chung-Kuan Cheng, University of California at
San Diego, La
J
olla,
CA
ICI
Analysis
of
Substrate Thermal Gradient
Effects
on Optimal
.44
Buffer
Insertion
Amir
H.
Ajami, Kaustav
Banerjee, Massoud Pedram
1C.2 A New Algorithm for Routing Tree Construction with Buffer Insertion
. 49
and Wire Sizing Under Obstacle Constraints
Xiaoping Tang, Ruiqi
Tian,
Hua
Xiang,
D.F.
Wong
1C.3 Bus Encoding to Prevent Crosstalk Delay
.57
Bret Victor, Kurt Keutzer
Session ID: Analog Macromodeling
Moderators: Rob A.
Rutenbar,
Carnegie Mellon University, Pittsburgh, PA
Henry Chang, Cadence Design Systems, Inc., San Jose, CA
1D.1 Behavioral Modeling of Analog Circuits by Wavelet Collocation Method.
. 65
Xin Li, Xuan
Zeng,
Dian
Zhou, Xieting Ling
1D.2 Simulation-Based Automatic Generation of Signomial and
.70
Posynomial Performance Models for Analog Integrated Circuit Sizing
Walter Daems, Georges Gielen, Willy
Sansen
1D3 Power Grid Transient Simulation in Linear Time Based on
.75
Transmission-Line-Modeling Alternating-Direction-Implicit Method
Yu-Min Lee, Charlie Chung-Ping Chen
Session 2A: Embedded Tutorial: Platform-Based Designs
Moderator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA
Session 2B: Embedded Tutorial: VLSI Microsystems: The Power of Many
Moderator:
Mattan
Komon,
Coventor, Inc., Cambridge, MA
Session
ЗА:
Sequential Synthesis
Moderators:
Hamid
Savoj, Magma Design Automation, Inc., Cupertino, CA
Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA
3A.1 Sequential SPFDs
.84
Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
3A.2 On the Optimization Power of Redundancy Addition and
.91
Removal Techniques for Sequential Circuits
Enrique
San Millán,
Luis Entrena, José
Alberto
Espejo
3A.3 Placement Driven Retiming with a Coupled Edge Timing Model
.95
Ingmar
Neumann, Wolfgang Kunz
3A.4 Solution of Parallel Language Equations for Logic Synthesis
.103
Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alex Petrenko,
Alberto L. Sangiovanni-Vincentelli
Session 3B: Compiler Techniques in System Level Design
Moderators:
Radu
Marculescu, Carnegie Mellon University, Pittsburgh, PA
Grant Martin, Cadence Design Systems, Inc., San Jose, CA
3B.1 CALiBeR: A Software Pipelining Algorithm for Clustered Embedded
. 112
VLIW Processors
Cagdas Akturan,
Margarida
F. J
acome
3B.2 Software-
Assisted
Cache
Replacement Mechanisms for Embedded
Systems
. 119
Prabhat Jain, Srinivas Devadas, Daniel
Engels,
Larry Rudolph
3B3 Instruction Generation for Hybrid
Reconfigurable
Systems
.127
Ryan Kastner,
Seda
Ogrenci-Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
Session 3C: Routing Architecture and Techniques for FPGAs
Moderators: Majid Sarrafzadeh, University of California, Los Angeles, CA
Rajeev Jay
aroman,
Хійпх,
Inc., San Jose, CA
3d
Interconnect Resource-Aware Placement for Hierarchical FPGAs
.132
Amit
Singh, Ganapathy Parthasarathy,
Małgorzata
Marek-Sadowska
3CJ2 A Router for Symmetrical FPGAs Based on Exact Routing Density
.137
Evaluation
Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
3CJ A Search-Based Bump-and-RefH Approach to Incremental Routing
.144
for ECO Applications in FPGAs
Vinay Verma, Shantanu Dutt
vu
Session 3D: Interconnect Performance
and Reliability Optimization
Moderators: David D. Ling, IBM Corp.
T J
Watson Research Center,
Yorktown
Heights, NY
Ken
Kundért,
Cadence Design Systems, Inc., San Jose, CA
3D.1 Area Minimization of Power Distribution Network using Efficient
.153
Nonlinear Programming Techniques
Xiaohai Wu, Xianlong Hong, Yici
Cai,
С. К.
Cheng,
Jun Gu,
Wayne
Dai
3D.2
Coupled Analysis of Electromigration Reliability
and Performance in
.158
U
LSI Signal Nets
Kaustav Banerjee,
Amit Mehrotra
3Đ.3
Compact Modeling and SPICE-Based Simulation for Electrothermal
.165
Analysis of Multilevel ULSI Interconnects
Ting-Yen Chiang, Kaustav Banerjee, Krishna C. Saraswat
Panel: Will Nanotechnology Change the Way We Design
.174
and Verify Systems?
Moderator: Andreas Kuehlmann, Cadence Berkeley Labs., Berkeley, CA
Robert W. Dutton, Paul Franzon, Seth C. Goldstein,
Philip Luekes, Eric Parker, Thomas
N.
Theis
Session 4A: Circuit Structure in Formal Verification
Moderators: Masahiro Fujita, University of Tokyo, Tokyo, Japan
Vigyan Singal,
Tempus
Fujit,
Berkeley, CA
4A.1
Min-
Area Retiming on Flexible Circuit Structures
.».176
Jason Baumgartner, Andreas Kuehlmann
4A.2 Verification of Integer Multipliers on the Arithmetic Bit Level.
. 183
Dominik Stoffel,
Wolfgang Kunz
4A3 Induction-Based Gate-Level Verification of Multipliers
.190
Ying-Tsai Chang, Kwang-Ting (Tim) Cheng
Session 4B: System Level Power and Performance Modeling
Moderators: Wayne Wolf,
Mediaworks
Technology,
Schaumberg,
IL
Preetì Panda,
Synopsys, Inc., Mountain View, CA
4B.1 An Assembly-Level Execution-Time Model for Pipelined Architectures
. . 195
G. Beltrame, C. Brandolese, W. Fornaciari, F.
Salice,
D.
Sciuto,
V. Triamú
4B.2 Improving Memory Energy using Access Pattern Classification
.201
Mahut Kandemir, UgurSezer, Victor Delaluz
vut
4B.3
System-Level Power/Performance Analysis of Portable Multimedia
.207
Systems Communicating Over Wireless Channels
Radu Marculescu,
Amit
Nandi, Luciano Lavagno,
Alberto L. Sangiovanni-Vincentelli
Session 4C: Topics in Physical Synthesis
Moderators: Andrew B. Kahng, University of California at San Diego, La
J
olla,
СА
Małgorzata Marek-Sadowska,
University of California,
Santa Barbara,
С А
4C.1 Congestion Aware Layout Driven Logic Synthesis
.216
Thomas Kutzschebauch, Leon
Stok
4C.2 Addressing the Tuning Closure Problem by Integrating Logic
.224
Optimization and Placement
Wilsin
Gosti,
Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli
4C.3 An Algorithm for Simultaneous Pin Assignment and Routing
.232
Hua
Xiang, Xiaoping Tang, D.F. Wong
Session 4D: Model Order Reduction
Moderators: Eli Chiprout, Intel Corp., Chandler, AZ
Andreas C. Cangellaris, University of Illinois,
Urbana,
IL
4D.1 Techniques for Including Dielectrics when Extracting Passive
.240
Low-Order Models of High Speed Interconnect
Luca
Daniel, Alberto
L
Sangiovanni-Vincentelli, Jacob White
4D.2 A Convex Programming Approach to Positive Real Rational
.245
Approximation
Carlos P.
Coelho,
Joel R. Phillips,
L
Miguel
Silveira
4D.3 A Trajectory Piecewise-Linear Approach to Model Order Reduction
.252
and Fast Simulation of Nonlinear Circuits and Micromachined Devices
Michal
Rewienski, Jacob White
Session 5A: Embedded Tutorial: Embedded Software and Systems
Moderators: Rolf Ernst, Technical University of Braunschweig,
Braunschweig, Germany
Francky
Catthoor, IMEC,
Leuven,
Belgium
5A.1 Low Power System Scheduling and Synthesis
.259
NirajK.Jha
5AJ Integral Design Representations for Embedded Systems
.264
Lothar
Thiele
5A.4 Optimisation Problems for Dynamic Concurrent Task-Based Systems
. 265
D. Verkest, P. Yang, C. Wong, P.
Marchai
їх
Session
5В:
Embedded Tutorial: CAD Solutions and Outstanding
Challenges for Mixed-Signal and RF
1С
Design
Moderator: Georges Gielen,
Katholieke
University,
Leuven,
Belgium
Domine
Leenaerts, Rob A.
Rutenbar,
Georges Gielen
.270
Session 6A: BDDs and SAT
Moderators: Alan J.
Ни,
University of British Columbia, Vancouver,
ВС,
Canada
Rajeev Ranjan, Real Intent, Santa Clara, CA
6A.1 Efficient Conflict Driven Learning in a Boolean Satisfiability Solver
.279
Lintao Zhang, Conor F. Madigan, Matthew H. Moskewicz, Sharad Malik
6A.2 Partition-Based Decision Heuristics for Image Computation
.286
using SAT and BDDs
Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
6A.3 Non-Linear Quantification Scheduling in Image Computation
.293
Pankaj Chauhan, Edmund M. Clarke, Somesh
J
ha, Jim
K ukula,
Tom Shiple, Helmut Veith, Dong Wang
Session 6B: Convergence of Abstractions in High-Level Synthesis
Moderators: Sandeep Shukla, University of California, Irvine, CA
Francky
Catthoor, IMEC,
Leuven,
Belgium
6B.1 Symbolic Algebra and Timing Driven Data-Flow Synthesis
.300
Armita Peymandoust, Giovanni
De Micheli
6B.2 Application-Driven Processor Design Exploration for Power-Performance
. . 306
Trade-Off Analysis
Diana Marculescu, Anoop Iyer
6B.3 A System for Synthesizing Optimized FPGA Hardware from
MATLAB
. 314
Malay Haldar, Anshuman Nayak, Alok Choudhary, Prith Banerjee
6B.4 Behavior-to-Placed
RTL
Synthesis with Performance-Driven
.320
Placement
Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi
Session 6C: Signal Integrity and Clock Design
Moderators: Cheng
-Кок
Koh, Purdue University, West Lafayette, IN
Tong
Gao,
Monterey Design Systems, Inc., Sunnyvale, CA
6C.1 Formulae and Applications of Interconnect Estimation Considering
.327
Shield Insertion and Net Ordering
James D.Z.
Ma, Le He
6C.2 Hybrid Structured Clock Network Construction
.333
Haihua
Su,
Sachin
S.
Sapatnekar
6C.3
CASh: A Novel "Clock as Shield" Design Methodology for Noise
.337
Immune Precharge-Evaluate Logic
Yonghee
Im, Kaushik
Roy
Session 6D: Analog Synthesis
Moderators:
Koen
Lampaert, Mindspeed Technology, Newport Beach, CA
Henry Chang, Cadence Design Systems, Inc., San Jose, CA
6D.1 The Sizing Rules Method for Analog Integrated Circuit Design
.343
H. Graeb,
S. Zízala,
J. Eckmueller, K. Antreich
6D.2 ASF: A Practical Simulation-Based Methodology for the Synthesis
.350
of Custom Analog Circuits
Michael J. Krasnicki, Rodney Phelps, James R. Heliums, Mark McClung,
Rob A.
Rutenbar,
L.
Richard Carley
6D.3 A Layout-Aware Synthesis Methodology for RF Circuits
.358
P. Vancorenland, G. Van
der Plas,
M.
Steyaert,
G.
Gielen,
W.
Sansen
Session 7A: Manufacturing Test: Stuck-at to Crosstalk
Moderators: Sujit
Dey,
University of California at San Diego,
La Joua,
С А
Yervant Zorian, LogicVision, Inc., San Jose, CA
7A.1 On Identifying Don't Care Inputs of Test Patterns for Combinational
.364
Circuits
Seiji Kajihara, Kohei Miyase
7A.2
REDI:
An Efficient Fault Oriented Procedure to Identify Redundant
.370
Faults in Combinational Logic Circuits
Chen Wang, Irith Pomeranz, SudhakarM. Ready
7A.3 Crosstalk Fault Detection by Dynamic
Idd
.375
Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota
Session 7B: Architecture Oriented Scheduling
Moderators: Miodrag Potkonjak, University of California, Los Angeles, CA
Kazutoshi Wakabayashi, NEC Corp., Kawasaki, Japan
7B.1 Color Permutation: An Iterative Algorithm for Memory Packing
.380
JianwenZhu, Edward S. Rogers, Sr.
7B.2 Constraint Satisfaction for Relative Location Assignment and Scheduling
. . 384
Carlos Alba-Pinto, Bart Mesman,
Jochen
Jess
7B3 A Super-Scheduler for Embedded
Reconfigurable
Systems
.391
5.
Ogrenci
Menük,
E. Bozorgzadeh, R.
Kastner,
M.
Sarrajzadeh
Session 7C: New
Techniques
in Routing
Moderators:
Jo Dale Carothers, University of Arizona, Tucson,
AZ
Amir
H. Farrahi, IBM Corp. TJ
Watson
Research
Center,
Yorktown
Heights, NY
7C.1 Multilevel Approach to Full-Chip Gridless Routing
.396
Jason Cong, Jie Fang,
У
an Zhang
7C.2 A Force-Directed Maze Router
.404
Fan
Mo, Abdallah
Tabbara, Robert K. Brayton
7C.3 Minimum-Buffered Routing of Non-Critical Nets for Slew Rate
.408
and Reliability Control
Charles Alpert, Andrew B. Kahng,
Bao
Liu, Ion Mandoiu, Alexander Zelikovsky
Session 7D: Issues in Substrate Coupling
Moderators:
Mattan
Komon,
Coventor, Inc., Cambridge, MA
Kenneth L· Shepard, Columbia University, New York, NY
7D.1 Highly Accurate Fast Methods for Extraction and Sparsification
.417
of Substrate Coupling Based on Low-Rank Approximation
Joe
Kanapka,
Jacob White
7D.2 Fast
3-D
Inductance Extraction in Lossy Multi-Layer Substrate
.424
Minqing Liu, Tiejun Yu, Wayne W.-M. Dai
7D.3 Simulation Approaches for Strongly Coupled Interconnect Systems
.430
Joel R. Phillips,
L
Miguel
Silveira
Session 8A: Combinational Optimization
Moderators: Olivier Coudert, Monterey Design Systems, Inc., Sunnyvale, CA
Tiziano Villa, Parades Labs., Rome, Italy
8A.1 BOOM-A Heuristic Boolean Minimizer
.439
Jan
Hlavièka, PetrFiser
8A.2 Faster SAT and Smaller BDDs via Common Function Structure
.443
FadiA. Aloul, IgorL. Markov,
Karem
A. Sakallah
8A3 Recursive Bipartitioning of BDDs for Performance Driven Synthesis
.449
of Pass Transistor Logic Circuits
Rupesh S. Shelar,
Sachin
S.
Sapatnekar
8A.4 A Probabilistic Constructive Approach to Optimization Problems
.453
Jennifer
L
Wong, Farinzaz Koushanfar, Seapahn Meguerdichian,
Miodrag Potkonjak
xu
Session
8В:
Real Time Scheduling and Performance Analysis
Moderators:
Pai
Chou,
University of California, Irvine, CA
Luciano
Lavagne,
Cadence
Berkeley Labs., Berkeley, CA
8B.1 Energy Efficient
Real-Time
Scheduling
.458
Amit
Sinha, Anantha P.
Chandrakasan
8B.2 Efficient Performance Estimation for General Real-Time Task Systems
. . . 464
Hongchao (Stephanie) Liu, Xiaobo (Sharon)
Ни
8B.3 Stars in VCC: Complementing Simulation with Worst-Case Analysis
.471
Felice Balarin
Session 8C: Power Analysis
Moderators: Anirudh Devgan, IBM Corp., Austin,
TX
Carlo
Guardini,
PDF Solutions, San Jose, CA
8C.1 Multigrid-Like Technique for Power Grid Analysis
.480
Joseph
N.
Kozhaya,
Sani
R.
Nassif, Farid
N.
Najm
8C.2 An Analytical High-Level Battery Model for Use in Energy Management.
. . 488
of Portable Electronic Systems
Daler
N.
Rakhmatov,
Sarma
B. K. Vrudhula
8C.3 Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization.
. 494
J.L·
Rossello,
Jawne
Segura
Session 8D: Timing and Noise Analysis
Moderators: Tim Burks, Magma Design Automation, Inc., Cupertino, CA
Florentin Dartu,
Intel Corp.,
Hillsboro,
OR
8D.1 A Symbolic Simulation-Based Methodology for Generating Black-Box
. 501
Timing Models of Custom Macrocells
Clayton McDonald, Randal E. Bryant
8D.2 On the Signal Bounding Problem in Timing Analysis
.507
Jin-Fuw Lee, D.L Ostapko, Jeffery Soreff, C.K. Wong
8D3 False-Noise Analysis using Logic Implications
.515
Alexey Glebov, Sergey Gavrilov, David Blaauw,
Suparnas
Sirichotiyakul,
ChanheeOh, Vladimir Zolotov
Session 9A: System Level Test and Reliability
Moderators:
Варі
Vinnakota, University of Minnesota, Minneapolis, MN
Seifi Kafihara, Kyushu Institute of Technology, Iizuka, Japan
9A.1 The Design and Optimization of
SOC
Test Solutions
.523
Erik
Larsson,
Zebo
Peng,
Gunnar Carlsson
лги
9A.2
Accurate CMOS Bridge Fault Modeling with Neural Network-Based
.531
VHDL Saboteurs
Don Shaw, Dhamin Al-Khalili, Come Rozon
9A.3 Algorithm Level Re-Computing
-
A Register Transfer Level
.537
Concurrent Error Detection Technique
Kaijie Wu, Ramesh Karri
Session 9B:
Pover
Issues in High Level Synthesis
Moderators: Sridevan Parameswaran, The University of New
South Wales, Kensington, Australia
NikilDutt, University of California, Irvine,
С А
9B.1 Transient Power Management Through High Level Synthesis
.545
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha, Ganesh Lakshminarayana
9B.2 An Integrated Data Path Optimization for Low Power Based
.553
on Network Flow Method
Chun-Gi Lyuh, Taewhan Kim, C.L. Liu
9B.3 What is the Limit of Energy Saving by Dynamic Voltage Scaling?
.560
GangQu
Session 9C: Advances in Placement
Moderators: Jason Cong, University of Calif ornia, Los Angeles,
С А
Patrick Groeneveld, Magma Design Automation, Inc., Cupertino, CA
9C.1 Local Search for Final Placement in VLSI Design
.565
Oluf Faroe, David Pisinger, Martin Zachariasen
9C.2 Congestion Reduction During Placement Based on Integer Programming.
. . 573
Xiaojian
Yang, Ryan Kastner,
Majid Sarrafzadeh
9C3 Direct Transistor-Level Layout for Digital Blocks
.577
Prakash Gopalakrishnan, Rob A.
Rutenbar
Session 9D: Interconnect Analysis and Extraction
Moderators: Dennis M. Sylvester, University of Michigan, Ann Arbor, MI
Mustafa
Celík,
Monterey Design Systems, Inc., Sunnyvale, CA
9D.1 Model Reduction of Variable-Geometry Interconnects using
.586
Variational Spectrally-Weighted Balanced Truncation
Payant
Heydari, Massoud Pedram
9D.2 Improving the Robustness of a Surface Integral Formulation for
.592
Wideband Impendance Extraction of
3D
Structures
Zhenhai Zhu, Jingfang Huang, Ben Song, Jacob White
9D3 Practical Considerations in RLCK Crosstalk Analysis
f
or Digital
.598
Integrated Circuits
Steven C. Chan, Kenneth L· Shepard
xiv
Session lOA:
Don't Care Optimization and Boolean Matching
Moderators: Yuji Kukimoto, Silicon Perspective Corp., Santa Clara, CA
Prabhakar Kudva, IBM Corp.
T J
Watson Research
Center,
Yorktown
Heights, NY
10A.1 Single-Pass Redundancy Addition and Removal
.606
Chih-Wei (Jim) Chang,
Małgorzata Marek-Sadowska
10A.2 Efficient Canonical Form for Boolean Matching of Complex
.610
Functions in Large Libraries
Jovanka Ciric,
Carl Sechen
10A.3 Compatible Observability Don't Cares Revisited
.618
R.K. Brayton
Session 10B: Power Saving Techniques for Embedded Processors
Moderators: Preeti Panda, Synopsys, Inc., Mountain View, CA
Tony Givargis, University of California, Irvine,
С А
10B.1 A Methodology for the Design of Application Specific Instruction
.625
Set Processors (ASEP) using the Machine Description Language LISA
Andreas Hoffmann, Oliver Schliebusch,
Achim
Nohl, Gunner
Braun,
Oliver
Wahlen, Heinrich Meyr
10B.2 Area and Power Reduction of Embedded DSP Systems using
.631
Instruction Compression and Re-Configurable Encoding
Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
10B.3 I-CoPES: Fast Instruction Code Placement for Embedded Systems
.635
to Improve Performance and Energy Efficiency
Sridevan Parameswaran,
Jörg Henkel
Session IOC: Embedded Tutorial:
1С
Power Distribution Challenges
Moderator: FaridNajm, University of Toronto, Toronto, ON, Canada
10C.1
1С
Power Distribution Challenges
.643
Sudhakar
Bobba,
Tyler Thorp, Kathirgamar Aingaran, Dean Liu
10C.2 Challenges in Power-Ground Integrity
.651
Shen Lin, Norman Chang
Session HA: Panel: Automatic Hierarchical Design: Fantasy or Reality?
Moderator: Rob A.
Rutenbar,
Carnegie Mellon University,
Pittsburghy
PA
НАЛ
Automatic Hierarchical Design: Fantasy or Reality?
.656
Olivier Coudert, Patrick Groeneveld, Juergen Koehl,
Scott Peterson, Vivek Raghavan, Naresh
Soni
xv |
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| author_facet | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
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| classification_rvk | SS 2001 |
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| discipline | Informatik |
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| spelling | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 2001 San José, Calif. Verfasser (DE-588)10038981-8 aut ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 IEEE ACM digest of technical papers Proceeding of the 2001 International Conference on Computer-Aided Design Piscatay, NJ IEEE [u.a.] 2001 XXV, 656 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 San Jose Calif. gnd-content CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009641108&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
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| subject_GND | (DE-588)4069794-0 (DE-588)1071861417 |
| title | ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA |
| title_alt | IEEE ACM digest of technical papers Proceeding of the 2001 International Conference on Computer-Aided Design |
| title_auth | ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA |
| title_exact_search | ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA |
| title_full | ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 |
| title_fullStr | ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 |
| title_full_unstemmed | ICCAD 2001 November 4 - 8, 2001, Doubletree Hotel, San Jose, CA IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 |
| title_short | ICCAD 2001 |
| title_sort | iccad 2001 november 4 8 2001 doubletree hotel san jose ca |
| title_sub | November 4 - 8, 2001, Doubletree Hotel, San Jose, CA |
| topic | CAD (DE-588)4069794-0 gnd |
| topic_facet | CAD Konferenzschrift 2001 San Jose Calif. |
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