Cross talk noise immune VLSI design using regular layout fabrics:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer Acad. Publ.
2001
|
| Schlagworte: | |
| Beschreibung: | XIX, 112 S. graph. Darst. |
| ISBN: | 079237407X |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV013963971 | ||
| 003 | DE-604 | ||
| 005 | 20020307 | ||
| 007 | t | ||
| 008 | 011018s2001 d||| |||| 00||| eng d | ||
| 020 | |a 079237407X |9 0-7923-7407-X | ||
| 035 | |a (OCoLC)46835363 | ||
| 035 | |a (DE-599)BVBBV013963971 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-703 | ||
| 050 | 0 | |a TK7874.75 | |
| 082 | 0 | |a 621.39/5 |2 21 | |
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 100 | 1 | |a Khatri, Sunil P. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Cross talk noise immune VLSI design using regular layout fabrics |c Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli |
| 264 | 1 | |a Boston [u.a.] |b Kluwer Acad. Publ. |c 2001 | |
| 300 | |a XIX, 112 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Crosstalk |x Prevention | |
| 650 | 4 | |a Integrated circuit layout | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Brayton, Robert K. |e Verfasser |4 aut | |
| 700 | 1 | |a Sangiovanni-Vincentelli, Alberto L. |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-009557066 | ||
Datensatz im Suchindex
| _version_ | 1804128813965115392 |
|---|---|
| any_adam_object | |
| author | Khatri, Sunil P. Brayton, Robert K. Sangiovanni-Vincentelli, Alberto L. |
| author_facet | Khatri, Sunil P. Brayton, Robert K. Sangiovanni-Vincentelli, Alberto L. |
| author_role | aut aut aut |
| author_sort | Khatri, Sunil P. |
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| building | Verbundindex |
| bvnumber | BV013963971 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75 |
| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4950 |
| ctrlnum | (OCoLC)46835363 (DE-599)BVBBV013963971 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV013963971 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:55:13Z |
| institution | BVB |
| isbn | 079237407X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009557066 |
| oclc_num | 46835363 |
| open_access_boolean | |
| owner | DE-703 |
| owner_facet | DE-703 |
| physical | XIX, 112 S. graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Kluwer Acad. Publ. |
| record_format | marc |
| spelling | Khatri, Sunil P. Verfasser aut Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli Boston [u.a.] Kluwer Acad. Publ. 2001 XIX, 112 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Crosstalk Prevention Integrated circuit layout Integrated circuits Very large scale integration Design and construction VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s DE-604 Brayton, Robert K. Verfasser aut Sangiovanni-Vincentelli, Alberto L. Verfasser aut |
| spellingShingle | Khatri, Sunil P. Brayton, Robert K. Sangiovanni-Vincentelli, Alberto L. Cross talk noise immune VLSI design using regular layout fabrics Crosstalk Prevention Integrated circuit layout Integrated circuits Very large scale integration Design and construction VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 |
| title | Cross talk noise immune VLSI design using regular layout fabrics |
| title_auth | Cross talk noise immune VLSI design using regular layout fabrics |
| title_exact_search | Cross talk noise immune VLSI design using regular layout fabrics |
| title_full | Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli |
| title_fullStr | Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli |
| title_full_unstemmed | Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli |
| title_short | Cross talk noise immune VLSI design using regular layout fabrics |
| title_sort | cross talk noise immune vlsi design using regular layout fabrics |
| topic | Crosstalk Prevention Integrated circuit layout Integrated circuits Very large scale integration Design and construction VLSI (DE-588)4117388-0 gnd |
| topic_facet | Crosstalk Prevention Integrated circuit layout Integrated circuits Very large scale integration Design and construction VLSI |
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