VLSI digital signal processing systems: design and implementation
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
Wiley
1999
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XX, 784 S. graph. Darst. |
| ISBN: | 0471241865 |
Internformat
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Datensatz im Suchindex
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| adam_text | VLSI DIGITAL SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION KESHAB
K. PARHI UNIVERSITY OF MINNESOTA A WILEY-INTERSCIENCE PUBLICATION JOHN
WILEY & SONS, INC. NEW YORK * CHICHESTER * WEINHEIM * BRISBANE *
SINGAPORE * TORONTO CONTENTS PREFACE XV 1 INTRODUCTION TO DIGITAL SIGNAL
PROCESSING SYSTEMS 1 1.1 INTRODUCTION 1 1.2 TYPICAL DSP ALGORITHMS 2 1.3
DSP APPLICATION DEMANDS AND SCALED CMOS TECHNOLOGIES 27 1.4
REPRESENTATIONS OF DSP ALGORITHMS 31 1.5 BOOK OUTLINE 40 REFERENCES 41 2
ITERATION BOUND 43 2.1 INTRODUCTION 43 2.2 DATA-FLOW GRAPH
REPRESENTATIONS 43 2.3 LOOP BOUND AND ITERATION BOUND 45 2.4 ALGORITHMS
FOR COMPUTING ITERATION BOUND 47 2.5 ITERATION BOUND OF MULTIRATE
DATA-FLOW GRAPHS 55 2.6 CONCLUSIONS 57 2.7 PROBLEMS 58 REFERENCES 61
CONTENTS PIPELINING AND PARALLEL PROCESSING 3.1 INTRODUCTION 3.2
PIPELINING OF FIR DIGITAL FILTERS 3.3 PARALLEL PROCESSING 3.4 PIPELINING
AND PARALLEL PROCESSING FOR LOW POWER 3.5 CONCLUSIONS 3.6 PROBLEMS
REFERENCES RETIMING 4.1 INTRODUCTION 4.2 DEFINITIONS AND PROPERTIES 4.3
SOLVING SYSTEMS OF INEQUALITIES 4.4 RETIMING TECHNIQUES 4.5 CONCLUSIONS
4.6 PROBLEMS REFERENCES UNFOLDING 5.1 INTRODUCTION 5.2 AN ALGORITHM FOR
UNFOLDING 5.3 PROPERTIES OF UNFOLDING 5.4 CRITICAL PATH, UNFOLDING, AND
RETIMING 5.5 APPLICATIONS OF UNFOLDING 5.6 CONCLUSIONS 5.7 PROBLEMS
REFERENCES FOLDING 6.1 INTRODUCTION 6.2 FOLDING TRANSFORMATION 6.3
REGISTER MINIMIZATION TECHNIQUES 6.4 REGISTER MINIMIZATION IN FOLDED
ARCHITECTURES 6.5 FOLDING OF MULTIRATE SYSTEMS 6.6 CONCLUSIONS 6.7
PROBLEMS REFERENCES 63 63 64 69 74 82 83 88 91 91 93 95 97 112 112 118
119 119 121 124 127 128 140 140 147 149 149 151 157 163 170 174 174 186
7 SYSTOLIC ARCHITECTURE DESIGN 189 CONTENTS IX 7.1 INTRODUCTION 189 7.2
SYSTOLIC ARRAY DESIGN METHODOLOGY 190 7.3 FIR SYSTOLIC ARRAYS 192 7.4
SELECTION OF SCHEDULING VECTOR 201 7.5 MATRIX-MATRIX MULTIPLICATION AND
2D SYSTOLIC ARRAY DESIGN 205 7.6 SYSTOLIC DESIGN FOR SPACE
REPRESENTATIONS CONTAINING DELAYS 210 7.7 CONCLUSIONS 213 7.8 PROBLEMS
213 REFERENCES 223 8 FAST CONVOLUTION 227 8.1 INTRODUCTION 227 8.2
COOK-TOOM ALGORITHM 228 8.3 WINOGRAD ALGORITHM 237 8.4 ITERATED
CONVOLUTION 244 8.5 CYCLIC CONVOLUTION 246 8.6 DESIGN OF FAST
CONVOLUTION ALGORITHM BY INSPECTION 250 8.7 CONCLUSIONS 251 8.8 PROBLEMS
251 REFERENCES 253 9 ALGORITHMIC STRENGTH REDUCTION IN FILTERS AND
TRANSFORMS 255 9.1 INTRODUCTION 255 9.2 PARALLEL FIR FILTERS 256 9.3
DISCRETE COSINE TRANSFORM AND INVERSE DCT 275 9.4 PARALLEL ARCHITECTURES
FOR RANK-ORDER FILTERS 285 9.5 CONCLUSIONS 297 9.6 PROBLEMS 297
REFERENCES 310 10 PIPELINED AND PARALLEL RECURSIVE AND ADAPTIVE FILTERS
313 10.1 INTRODUCTION 313 10.2 PIPELINE INTERLEAVING IN DIGITAL FILTERS
314 10.3 PIPELINING IN LST-ORDER MR DIGITAL FILTERS 320 10.4 PIPELINING
IN HIGHER-ORDER MR DIGITAL FILTERS 325 10.5 PARALLEL PROCESSING FOR IIR
FILTERS 339 10.6 COMBINED PIPELINING AND PARALLEL PROCESSING FOR IIR
FILTERS 345 X CONTENTS 10.7 LOW-POWER IIR FILTER DESIGN USING PIPELINING
AND PARALLEL PROCESSING 348 10.8 PIPELINED ADAPTIVE DIGITAL FILTERS 351
10.9 CONCLUSIONS 367 10.10 PROBLEMS 367 REFERENCES 374 11 SCALING AND
ROUNDOFF NOISE 377 11.1 INTRODUCTION 377 11.2 SCALING AND ROUNDOFF NOISE
. 378 11.3 STATE VARIABLE DESCRIPTION OF DIGITAL FILTERS 382 11.4
SCALING AND ROUNDOFF NOISE COMPUTATION 386 11.5 ROUNDOFF NOISE IN
PIPELINED IIR FILTERS 391 11.6 ROUNDOFF NOISE COMPUTATION USING STATE
VARIABLE DESCRIPTION 403 11.7 SLOW-DOWN, RETIMING, AND PIPELINING 405
11.8 CONCLUSIONS 410 11.9 PROBLEMS 410 REFERENCES 419 12 DIGITAL LATTICE
FILTER STRUCTURES 421 12.1 INTRODUCTION 421 12.2 SCHUR ALGORITHM 422
12.3 DIGITAL BASIC LATTICE FILTERS 429 12.4 DERIVATION OF ONE-MULTIPLIER
LATTICE FILTER 437 12.5 DERIVATION OF NORMALIZED LATTICE FILTER 444 12.6
DERIVATION OF SCALED-NORMALIZED LATTICE FILTER 447 12.7 ROUNDOFF NOISE
CALCULATION IN LATTICE FILTERS 454 12.8 PIPELINING OF LATTICE IIR
DIGITAL FILTERS 458 12.9 DESIGN EXAMPLES OF PIPELINED LATTICE FILTERS
464 12.10 LOW-POWER CMOS LATTICE IIR FILTERS 469 12.11 CONCLUSIONS 470
12.12 PROBLEMS 470 REFERENCES 474 13 BIT-LEVEL ARITHMETIC ARCHITECTURES
477 13.1 INTRODUCTION 477 13.2 PARALLEL MULTIPLIERS 478 13.3 INTERLEAVED
FLOOR-PLAN AND BIT-PLANE-BASED DIGITAL FILTERS 489 CONTENTS XI 13.4
BIT-SERIAL MULTIPLIERS 490 13.5 BIT-SERIAL FILTER DESIGN AND
IMPLEMENTATION 499 13.6 CANONIC SIGNED DIGIT ARITHMETIC 505 13.7
DISTRIBUTED ARITHMETIC 511 13.8 CONCLUSIONS 518 13.9 PROBLEMS 518
REFERENCES 527 14 REDUNDANT ARITHMETIC 529 14.1 INTRODUCTION 529 14.2
REDUNDANT NUMBER REPRESENTATIONS 530 14.3 CARRY-FREE RADIX-2 ADDITION
AND SUBTRACTION 531 14.4 HYBRID RADIX-4 ADDITION 536 14.5 RADIX-2 HYBRID
REDUNDANT MULTIPLICATION ARCHITECTURES 540 14.6 DATA FORMAT CONVERSION
545 14.7 REDUNDANT TO NONREDUNDANT CONVERTER 547 14.8 CONCLUSIONS 551
14.9 PROBLEMS 552 REFERENCES 555 15 NUMERICAL STRENGTH REDUCTION 559
15.1 INTRODUCTION 559 15.2 SUBEXPRESSION ELIMINATION 560 15.3 MULTIPLE
CONSTANT MULTIPLICATION 560 15.4 SUBEXPRESSION SHARING IN DIGITAL
FILTERS 566 15.5 ADDITIVE AND MULTIPLICATIVE NUMBER SPLITTING 574 15.6
CONCLUSIONS 583 15.7 PROBLEMS 583 REFERENCES 589 16 SYNCHRONOUS, WAVE,
AND ASYNCHRONOUS PIPELINES 591 16.1 INTRODUCTION 591 16.2 SYNCHRONOUS
PIPELINING AND CLOCKING STYLES 593 16.3 CLOCK SKEW AND CLOCK
DISTRIBUTION IN BIT-LEVEL PIPELINED VLSI DESIGNS 601 16.4 WAVE
PIPELINING 606 16.5 CONSTRAINT SPACE DIAGRAM AND DEGREE OF WAVE
PIPELINING 612 16.6 IMPLEMENTATION OF WAVE-PIPELINED SYSTEMS 614 16.7
ASYNCHRONOUS PIPELINING 619 XII CONTENTS 16.8 SIGNAL TRANSITION GRAPHS
622 16.9 USE OF STG TO DESIGN INTERCONNECTION CIRCUITS 626 16.10
IMPLEMENTATION OF COMPUTATIONAL UNITS 631 16.11 CONCLUSIONS 640 16.12
PROBLEMS 640 REFERENCES 643 17 LOW-POWER DESIGN 645 17.1 INTRODUCTION
645 17.2 THEORETICAL BACKGROUND 648 17.3 SCALING VERSUS POWER
CONSUMPTION 650 17.4 POWER ANALYSIS 652 17.5 POWER REDUCTION TECHNIQUES
662 17.6 POWER ESTIMATION APPROACHES 671 17.7 CONCLUSIONS 688 17.8
PROBLEMS 688 REFERENCES 692 18 PROGRAMMABLE DIGITAL SIGNAL PROCESSORS
695 18.1 INTRODUCTION 695 18.2 EVOLUTION OF PROGRAMMABLE DIGITAL SIGNAL
PROCESSORS 696 18.3 IMPORTANT FEATURES OF DSP PROCESSORS 697 18.4 DSP
PROCESSORS FOR MOBILE AND WIRELESS COMMUNICATIONS 703 18.5 PROCESSORS
FOR MULTIMEDIA SIGNAL PROCESSING 704 18.6 CONCLUSIONS 714 REFERENCES 714
APPENDIX A: SHORTEST PATH ALGORITHMS 717 A.I INTRODUCTION .- 717 A.2 THE
BELLMAN-FORD ALGORITHM 718 A.3 THE FLOYD-WARSHALL ALGORITHM 720 A.4
COMPUTATIONAL COMPLEXITIES 721 REFERENCES 722 APPENDIX B: SCHEDULING AND
ALLOCATION TECHNIQUES 723 B.I INTRODUCTION 723 B.2
ITERATIVE/CONSTRUCTIVE SCHEDULING ALGORITHMS 725 B.3 TRANSFORMATIONAL
SCHEDULING ALGORITHMS 729 B.4 INTEGER LINEAR PROGRAMMING MODELS 738
CONTENTS XIII REFERENCES 741 APPENDIX C: EUCLIDEAN GCD ALGORITHM 743 C.I
INTRODUCTION 743 C.2 EUCLIDEAN GCD ALGORITHM FOR INTEGERS 743 C.3
EUCLIDEAN GCD ALGORITHM FOR POLYNOMIALS 745 APPENDIX D: ORTHONORMALITY
OF SCHUR POLYNOMIALS 747 D.I ORTHOGONALITY OF SCHUR POLYNOMIALS 747 D.2
ORTHONORMALITY OF SCHUR POLYNOMIALS 749 APPENDIX E: FAST BINARY ADDERS
AND MULTIPLIERS 753 E.I INTRODUCTION 753 E.2 MULTIPLEXER-BASED FAST
BINARY ADDERS 753 E.3 WALLACE TREE AND DADDA MULTIPLIER 758 REFERENCES
761 APPENDIX F: SCHEDULING IN BIT-SERIAL SYSTEMS 763 F.I INTRODUCTION
763 F.2 OUTLINE OF THE SCHEDULING ALGORITHM 764 F.3 MINIMUM COST
SOLUTION 766 F.4 SCHEDULING OF EDGES WITH DELAYS 768 REFERENCES 769
APPENDIX G: COEFFICIENT QUANTIZATION IN FIR FILTERS 771 G.I INTRODUCTION
771 G.2 NUS QUANTIZATION ALGORITHM 771 REFERENCES 774 INDEX 775
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| isbn | 0471241865 |
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| spelling | Parhi, Keshab K. Verfasser aut VLSI digital signal processing systems design and implementation Keshab K. Parhi New York [u.a.] Wiley 1999 XX, 784 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Digitale Signalverarbeitung (DE-588)4113314-6 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Digitale Signalverarbeitung (DE-588)4113314-6 s VLSI (DE-588)4117388-0 s DE-604 HEBIS Datenaustausch Darmstadt application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009525691&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Parhi, Keshab K. VLSI digital signal processing systems design and implementation Digitale Signalverarbeitung (DE-588)4113314-6 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4113314-6 (DE-588)4117388-0 |
| title | VLSI digital signal processing systems design and implementation |
| title_auth | VLSI digital signal processing systems design and implementation |
| title_exact_search | VLSI digital signal processing systems design and implementation |
| title_full | VLSI digital signal processing systems design and implementation Keshab K. Parhi |
| title_fullStr | VLSI digital signal processing systems design and implementation Keshab K. Parhi |
| title_full_unstemmed | VLSI digital signal processing systems design and implementation Keshab K. Parhi |
| title_short | VLSI digital signal processing systems |
| title_sort | vlsi digital signal processing systems design and implementation |
| title_sub | design and implementation |
| topic | Digitale Signalverarbeitung (DE-588)4113314-6 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Digitale Signalverarbeitung VLSI |
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