Verfügbarkeit: An introduction to mixed signal IC test and measurement

An introduction to mixed signal IC test and measurement:

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Bibliographische Detailangaben
Hauptverfasser:	Burns, Mark (VerfasserIn), Roberts, Gordon W. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	New York, NY [u.a.] Oxford Univ. Press 2001
Schriftenreihe:	The Oxford series in electrical and computer engineering
Schlagworte:	Integrated circuits > Testing Mixed signal circuits > Testing Testen Integrierte Schaltung
Online-Zugang:	Publisher description Table of contents only Inhaltsverzeichnis
Beschreibung:	XX, 684 S. graph. Darst.
ISBN:	0195140168 9780195140163

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adam_text	AN INTRODUCTION TO MIXED-SIGNAL IC TEST AND MEASUREMENT MARK BURNS TEXAS INSTRUMENTS, INCORPORATED GORDON W. ROBERTS MCGILL UNIVERSITY NEW YORK OXFORD OXFORD UNIVERSITY PRESS 2001 CONTENTS PREFACE XVII CHAPTER 1: OVERVIEW OF MIXED-SIGNAL TESTING 1.1 MIXED-SIGNAL CIRCUITS 1 1.1.1 ANALOG, DIGITAL, OR MIXED-SIGNAL? 1 1.1.2 COMMON TYPES OF ANALOG AND MIXED-SIGNAL CIRCUITS 1.1.3 APPLICATIONS OF MIXED-SIGNAL CIRCUITS 3 1.2 WHY TEST MIXED-SIGNAL DEVICES? 5 1.2.1 THE CMOS FABRICATION PROCESS 5 1.2.2 REAL-WORLD CIRCUITS 5 1.2.3 WHAT IS A TEST ENGINEER? 8 1.3 POST-SILICON PRODUCTION FLOW 10 1.3.1 TEST AND PACKAGING 10 1.3.2 CHARACTERIZATION VERSUS PRODUCTION TESTING 1 1 1.4 TEST AND DIAGNOSTIC EQUIPMENT 11 1.4.1 AUTOMATED TEST EQUIPMENT 11 1.4.2 WAFER PROBERS 13 1.4.3 HANDLERS 13 1.4.4 E-BEAM PROBERS 14 1.4.5 FOCUSED ION BEAM EQUIPMENT 15 1.4.6 FORCED-TEMPERATURE SYSTEMS 15 1.5 NEW PRODUCT DEVELOPMENT 16 1.5.1 CONCURRENT ENGINEERING 16 1.6 MIXED-SIGNAL TESTING CHALLENGES 17 1.6.1 TIME TO MARKET 18 1.6.2 ACCURACY, REPEATABILITY, AND CORRELATION 18 1.6.3 ELECTROMECHANICAL FIXTURING CHALLENGES 18 1.6.4 ECONOMICS OF PRODUCTION TESTING 19 CHAPTER 2: THE TEST SPECIFICATION PROCESS 2.1 DEVICE DATA SHEETS 23 2.1.1 PURPOSE OF A DATA SHEET 23 2.1.2 STRUCTURE OF A DATA SHEET 24 2.1.3 ELECTRICAL CHARACTERISTICS 27 2.2 GENERATING THE TEST PLAN 31 2.2.1 TO PLAN OR NOT TO PLAN 31 VI CONTENTS 2.2.2 STRUCTURE OF A TEST PLAN 35 2.2.3 DESIGN SPECIFICATIONS VERSUS PRODUCTION TEST SPECIFICATIONS 36 2.2.4 CONVERTING THE DATA SHEET INTO A TEST PLAN 37 2.3 COMPONENTS OF A TEST PROGRAM 38 2.3.1 TEST PROGRAM STRUCTURE 38 2.3.2 TEST CODE AND DIGITAL PATTERNS 38 2.3.3 BINNING 40 2.3.4 TEST SEQUENCE CONTROL 40 2.3.5 WAVEFORM CALCULATIONS AND OTHER INITIALIZATIONS 41 2.3.6 FOCUSED CALIBRATIONS AND DIB CHECKERS 41 2.3.7 CHARACTERIZATION CODE 42 2.3.8 SIMULATION CODE 42 2.3.9 "DEBUGGABILITY" 42 2.4 SUMMARY 43 CHAPTER 3: DC AND PARAMETRIC MEASUREMENTS 3.1 CONTINUITY 45 3.1.1 PURPOSE OF CONTINUITY TESTING 45 3.1.2 CONTINUITY TEST TECHNIQUE 46 3.1.3 SERIAL VERSUS PARALLEL CONTINUITY TESTING 48 3.2 LEAKAGE CURRENTS 50 3.2.1 PURPOSE OF LEAKAGE TESTING 50 3.2.2 LEAKAGE TEST TECHNIQUE 50 3.2.3 SERIAL VERSUS PARALLEL LEAKAGE TESTING 51 3.3 POWER SUPPLY CURRENTS 51 3.3.1 IMPORTANCE OF SUPPLY CURRENT TESTS 51 3.3.2 TEST TECHNIQUES 51 3.4 DC REFERENCES AND REGULATORS 52 3.4.1 VOLTAGE REGULATORS 52 3.4.2 VOLTAGE REFERENCES 55 3.4.3 TRIMMABLE REFERENCES 55 3.5 IMPEDANCE MEASUREMENTS 56 3.5.1 INPUT IMPEDANCE 56 3.5.2 OUTPUT IMPEDANCE 58 3.5.3 DIFFERENTIAL IMPEDANCE MEASUREMENTS 59 3.6 DC OFFSET MEASUREMENTS 60 3.6.1 VMID AND ANALOG GROUND 60 3.6.2 DC TRANSFER CHARACTERISTICS (GAIN AND OFFSET) 60 3.6.3 OUTPUT OFFSET VOLTAGE (FO) 61 3.6.4 SINGLE-ENDED, DIFFERENTIAL, AND COMMON-MODE OFFSETS 62 3.6.5 INPUT OFFSET VOLTAGE (V O S) 64 3.7 DC GAIN MEASUREMENTS 65 3.7.1 CLOSED-LOOP GAIN 65 3.7.2 OPEN-LOOP GAIN 68 3.8 DC POWER SUPPLY REJECTION RATIO 71 3.8.1 DC POWER SUPPLY SENSITIVITY 71 3.8.2 DC POWER SUPPLY REJECTION RATIO 72 CONTENTS VII 3.9 DC COMMON-MODE REJECTION RATIO 72 3.9.1 CMRROFOPAMPS 72 3.9.2 CMRR OF DIFFERENTIAL GAIN STAGES 75 3.10 COMPARATOR DC TESTS 77 3.10.1 INPUT OFFSET VOLTAGE 77 3.10.2 THRESHOLD VOLTAGE 78 3.10.3 HYSTERESIS 78 3.11 VOLTAGE SEARCH TECHNIQUES 79 3.11.1 BINARY SEARCHES VERSUS STEP SEARCHES 79 3.11.2 LINEAR SEARCHES 80 3.12 DC TESTS FOR DIGITAL CIRCUITS 82 3.12.1 I M /IIL 82 3.12.2 V IH IV IL 82 3.12.3 VOHIVOL 82 3.12.4 IOHIIOL' 82 3.12.5 IOSH AND IOSL SHORT CIRCUIT CURRENT 82 3.13 SUMMARY 83 CHAPTER 4: MEASUREMENT ACCURACY 4.1 TERMINOLOGY 87 4.1.1 ACCURACY AND PRECISION 87 4.1.2 SYSTEMATIC ERRORS 88 4.1.3 RANDOM ERRORS 88 4.1.4 RESOLUTION (QUANTIZATION ERROR) 88 4.1.5 REPEATABILITY 89 4.1.6 STABILITY 90 4.1.7 CORRELATION 91 4.1.8 REPRODUCIBILITY 92 4.2 CALIBRATIONS AND CHECKERS 93 4.2.1 TRACEABILITY TO STANDARDS 93 4.2.2 HARDWARE CALIBRATION 93 4.2.3 SOFTWARE CALIBRATION 93 4.2.4 SYSTEM CALIBRATIONS AND CHECKERS 96 4.2.5 FOCUSED INSTRUMENT CALIBRATIONS 97 4.2.6 FOCUSED DIB CIRCUIT CALIBRATIONS 101 4.2.7 DIB CHECKERS 102 4.2.8 TESTER SPECIFICATIONS 103 4.3 DEALING WITH MEASUREMENT ERROR 106 4.3.1 FILTERING 106 4.3.2 AVERAGING 111 4.3.3 GUARDBANDING 113 4.4 BASIC DATA ANALYSIS 114 4.4.1 DATALOGS 114 4.4.2 HISTOGRAMS 115 4.4.3 NOISE, TEST TIME, AND YIELD 118 4.5 SUMMARY 120 VIII CONTENTS CHAPTER 5: TESTER HARDWARE 5.1 MIXED-SIGNAL TESTER OVERVIEW 123 5.1.1 GENERAL-PURPOSE TESTERS VERSUS FOCUSED BENCH EQUIPMENT 123 5.1.2 GENERIC TESTER ARCHITECTURE 123 5.2 DC RESOURCES 125 5.2.1 GENERAL-PURPOSE MULTIMETERS 125 5.2.2 GENERAL-PURPOSE VOLTAGE/CURRENT SOURCES 127 5.2.3 PRECISION VOLTAGE REFERENCES AND USER SUPPLIES 128 5.2.4 CALIBRATION SOURCE 128 5.2.5 RELAY MATRICES 128 5.2.6 RELAY CONTROL LINES 130 5.3 DIGITAL SUBSYSTEM 131 5.3.1 DIGITAL VECTORS 131 5.3.2 DIGITAL SIGNALS 131 5.3.3 SOURCE MEMORY' 132 5.3.4 CAPTURE MEMORY 132 5.3.5 PIN CARD ELECTRONICS 134 5.3.6 TIMING AND FORMATTING ELECTRONICS 136 5.4 AC SOURCE AND MEASUREMENT 139 5.4. 1 AC CONTINUOUS WAVE SOURCE AND AC METER 139 5.4.2 ARBITRARY WAVEFORM GENERATORS 139 5.4.3 WAVEFORM DIGITIZERS 140 5.4.4 CLOCKING AND SYNCHRONIZATION 141 5.5 TIME MEASUREMENT SYSTEM 141 5.5.1 TIME MEASUREMENTS 141 5.5.2 TIME MEASUREMENT INTERCONNECTS 142 5.6 COMPUTING HARDWARE 143 5.6.1 USER COMPUTER 143 5.6.2 TESTER COMPUTER 144 5.6.3 ARRAY PROCESSORS AND DISTRIBUTED DIGITAL SIGNAL PROCESSORS 144 5.6.4 NETWORK CONNECTIVITY 144 5.7 SUMMARY 144 CHAPTER 6: SAMPLING THEORY 6.1 ANALOG MEASUREMENTS USING DSP 147 6.1.1 TRADITIONAL VERSUS DSP-BASED TESTING OF AC PARAMETERS 147 6.2 SAMPLING AND RECONSTRUCTION 148 6.2.1 USE OF SAMPLING AND RECONSTRUCTION IN MIXED-SIGNAL TESTING 148 6.2.2 SAMPLING: CONTINUOUS-TIME AND DISCRETE-TIME REPRESENTATION 149 6.2.3 RECONSTRUCTION 152 6.2.4 THE SAMPLING THEOREM AND ALIASING 159 6.2.5 QUANTIZATION EFFECTS 161 6.2.6 SAMPLING JITTER 166 6.3 REPETITIVE SAMPLE SETS 170 6.3.1 FINITE AND INFINITE SAMPLE SETS 170 6.3.2 COHERENT SIGNALS AND NONCOHERENT SIGNALS 171 CONTENTS IX 6.3.3 PEAK-TO-RMS CONTROL IN COHERENT MULTITONES 173 6.3.4 SPECTRAL BIN SELECTION 175 6.4 SYNCHRONIZATION OF SAMPLING SYSTEMS 179 6.4.1 SIMULTANEOUS TESTING OF MULTIPLE SAMPLING SYSTEMS 179 6.4.2 ATE CLOCK SOURCES 181 6.4.3 THE CHALLENGE OF SYNCHRONIZATION 183 6.5 SUMMARY 184 CHAPTER 7: DSP-BASED TESTING 7.1 ADVANTAGES OF DSP-BASED TESTING 189 7.1.1 REDUCED TEST TIME 189 7.1.2 SEPARATION OF SIGNAL COMPONENTS 189 7.1.3 ADVANCED SIGNAL MANIPULATIONS 190 7.2 DIGITAL SIGNAL PROCESSING 190 7.2.1 DSP AND ARRAY PROCESSING 190 7.2.2 FOURIER ANALYSIS OF PERIODIC SIGNALS 191 7.2.3 THE TRIGONOMETRIC FOURIER SERIES 192 7.2.4 THE DISCRETE-TIME FOURIER SERIES 195 7.2.5 COMPLETE FREQUENCY SPECTRUM 205 7.2.6 TIME AND FREQUENCY DENORMALIZATION 210 7.2.7 COMPLEX FORM OF THE DTFS 211 7.3 DISCRETE-TIME TRANSFORMS 213 7.3.1 THE DISCRETE FOURIER TRANSFORM 213 7.3.2 THE FAST FOURIER TRANSFORM 216 7.3.3 INTERPRETING THE FFT OUTPUT 218 7.4 THE INVERSE FFT 230 7.4.1 EQUIVALENCE OF TIME-AND FREQUENCY-DOMAIN INFORMATION 230 7.4.2 PARSEVAL'S THEOREM 232 7.4.3 APPLICATIONS OF THE INVERSE FFT 233 7.4.4 FREQUENCY-DOMAIN FILTERING 234 7.4.5 NOISE WEIGHTING 239 7.5 SUMMARY 240 APPENDIX A.7.1 241 CHAPTER 8: ANALOG CHANNEL TESTING 8.1 OVERVIEW 249 8.1.1 TYPES OF ANALOG CHANNELS 249 8.1.2 TYPES OF AC PARAMETRIC TESTS 250 8.1.3 REVIEW OF LOGARITHMIC OPERATIONS 250 8.2 GAIN AND LEVEL TESTS 251 8.2.1 ABSOLUTE VOLTAGE LEVELS 251 8.2.2 ABSOLUTE GAIN AND GAIN ERROR 256 8.2.3 GAIN TRACKING ERROR 258 8.2.4 PGA GAIN TESTS 260 8.2.5 FREQUENCY RESPONSE 265 CONTENTS 8.3 PHASE TESTS 273 8.3.1 PHASE RESPONSE 273 8.3.2 GROUP DELAY AND GROUP DELAY DISTORTION 278 8.4 DISTORTION TESTS 280 8.4.1 SIGNAL TO HARMONIC DISTORTION 280 8.4.2 INTEL-MODULATION DISTORTION 283 8.5 SIGNAL REJECTION TESTS 284 8.5.1 COMMON-MODE REJECTION RATIO 284 8.5.2 POWER SUPPLY REJECTION AND POWER SUPPLY REJECTION RATIO 287 8.5.3 CHANNEL-TO-CHANNEL CROSSTALK 289 8.5.4 CLOCK AND DATA FEEDTHROUGH 293 8.6 NOISE TESTS 293 8.6.1 NOISE 293 8.6.2 IDLE CHANNEL NOISE 294 8.6.3 SIGNAL TO NOISE, SIGNAL TO NOISE AND DISTORTION 296 8.6.4 SPURIOUS FREE DYNAMIC RANGE 298 8.6.5 WEIGHTING FILTERS 300 8.7 SIMULATION OF ANALOG CHANNEL TESTS 304 8.7.1 MATLAB MODEL OF AN ANALOG CHANNEL 304 8.8 SUMMARY 308 CHAPTER 9: SAMPLED CHANNEL TESTING 9.1 OVERVIEW 315 9.1.1 WHAT ARE SAMPLED CHANNELS? 315 9.1.2 EXAMPLES OF SAMPLED CHANNELS 315 9.1.3 TYPES OF SAMPLED CHANNELS 318 9.2 SAMPLING CONSIDERATIONS 320 9.2.1 DUT SAMPLING RATE CONSTRAINTS 320 9.2.2 DIGITAL SIGNAL SOURCE AND CAPTURE 321 9.2.3 SIMULTANEOUS DAC AND ADC CHANNEL TESTING 326 9.2.4 MISMATCHED FUNDAMENTAL FREQUENCIES 330 9.2.5 UNDERSAMPLING 333 9.2.6 RECONSTRUCTION EFFECTS IN AWGS, DACS, AND OTHER SAMPLED-DATA CIRCUITS 335 9.3 ENCODING AND DECODING 338 9.3.1 SIGNAL CREATION AND ANALYSIS 338 9.3.2 DATA FORMATS 339 9.3.3 INTRINSIC ERRORS 344 9.4 SAMPLED CHANNEL TESTS 350 9.4.1 SIMILARITY TO ANALOG CHANNEL TESTS 350 9.4.2 ABSOLUTE LEVEL, ABSOLUTE GAIN, GAIN ERROR, AND GAIN TRACKING 351 9.4.3 FREQUENCY RESPONSE 356 9.4.4 PHASE RESPONSE (ABSOLUTE PHASE SHIFT) 359 9.4.5 GROUP DELAY AND GROUP DELAY DISTORTION 360 9.4.6 SIGNAL TO HARMONIC DISTORTION, INTENNODULATION DISTORTION 360 9.4.7 CROSSTALK 361 9.4.8 CMRR 362 CONTENTS XI 9.4.9 PSRANDPSRR 362 9.4.10 SIGNAL-TO-NOISE RATIO AND ENOB 363 9.4.11 IDLE CHANNEL NOISE 363 9.5 SUMMARY 364 CHAPTER 10: FOCUSED CALIBRATIONS 10.1 OVERVIEW 369 10.1.1 TRACEABILITY TO NATIONAL STANDARDS 369 10.1.2 WHY ARE FOCUSED CALIBRATIONS NEEDED? 370 10.1.3 TYPES OF FOCUSED CALIBRATIONS 372 10.1.4 MECHANICS OF FOCUSED CALIBRATION 372 10.1.5 PROGRAM STRUCTURE 375 10.2 DC CALIBRATIONS 376 10.2.1 DC OFFSET CALIBRATION 376 10.2.2 DC GAIN AND OFFSET CALIBRATIONS 378 10.2.3 CASCADING DC OFFSET AND GAIN CALIBRATIONS 380 10.3 AC AMPLITUDE CALIBRATIONS 382 10.3.1 CALIBRATING AWGS AND DIGITIZERS 382 10.3.2 LOW-LEVEL AWG AND DIGITIZER AMPLITUDE CALIBRATIONS 389 10.3.3 AMPLITUDE CALIBRATIONS FOR ADC AND DAC TESTS 390 10.4 OTHER AC CALIBRATIONS 392 10.4.1 PHASE SHIFTS 392 10.4.2 DIGITIZER AND AWG SYNCHRONIZATION 396 10.4.3 DAC AND ADC PHASE SHIFTS 396 10.4.4 DISTORTION TESTS 396 10.4.5 NOISE TESTS 397 10.5 ERROR CANCELLATION TECHNIQUES 397 10.5.1 AVOIDING ABSOLUTE CALIBRATION 397 10.5.2 GAIN AND PHASE MATCHING 397 10.5.3 DIFFERENTIAL GAIN AND DIFFERENTIAL PHASE 399 10.6 SUMMARY 400 CHAPTER 11: DAC TESTING 11.1 BASICS OF CONVERTER TESTING 403 11.1.1 INTRINSIC PARAMETERS VERSUS TRANSMISSION PARAMETERS 403 11.1.2 COMPARISON OF DACS AND ADCS 404 11.1.3 DAC FAILURE MECHANISMS 405 11.2 BASIC DC TESTS 405 11.2.1 CODE-SPECIFIC PARAMETERS 405 11.2.2 FULL-SCALE RANGE 406 11.2.3 DC GAIN, GAIN ERROR, OFFSET, AND OFFSET ERROR 406 11.2.4 LSB STEP SIZE 409 11.2.5 DCPSS 410 11.3 TRANSFER CURVE TESTS 410 11.3.1 ABSOLUTE ERROR 410 11.3.2 MONOTONICITY 412 XII CONTENTS 11.3.3 DIFFERENTIAL NONLINEARITY 412 11.3.4 INTEGRAL NONLINEARITY 416 11.3.5 PARTIAL TRANSFER CURVES 419 11.3.6 MAJOR CARRIER TESTING 420 11.3.7 OTHER SELECTED-CODE TECHNIQUES 423 11.4 DYNAMIC DAC TESTS 424 11.4.1 CONVERSION TIME (SETTLING TIME) 424 11.4.2 OVERSHOOT AND UNDERSHOOT 426 11.4.3 RISE TIME AND FALL TIME 426 11.4.4 DAC-TO-DAC SKEW 426 11.4.5 GLITCH ENERGY (GLITCH IMPULSE) 427 11.4.6 CLOCK AND DATA FEEDTHROUGH 428 11.5 DAC ARCHITECTURES 428 1L5.1 RESISTIVE DIVIDER DACS 428 11.5.2 BINARY-WEIGHTED DACS 430 11.5.3 PWMDACS 431 11.5.4 SIGMA-DELTA DACS 433 11.5.5 COMPANDED DACS 434 11.5.6 HYBRID DAC ARCHITECTURES 435 11.6 TESTS FOR COMMON DAC APPLICATIONS 435 11.6.1 DC REFERENCES 435 11.6.2 AUDIO RECONSTRUCTION 436 11.6.3 DATA MODULATION 436 11.6.4 VIDEO SIGNAL GENERATORS 436 11.7 SUMMARY 437 APPENDIX A.11.1 437 CHAPTER 12: ADC TESTING 12.1 ADC TESTING VERSUS DAC TESTING 447 12.1.1 COMPARISON OF DACS AND ADCS 447 12.1.2 STATISTICAL BEHAVIOR OF ADCS 448 12.2 ADC CODE EDGE MEASUREMENTS 454 12.2.1 EDGE CODE TESTING VERSUS CENTER CODE TESTING 454 12.2.2 STEP SEARCH AND BINARY SEARCH METHODS 455 12.2.3 SERVO METHOD 455 12.2.4 LINEAR RAMP HISTOGRAM METHOD 456 12.2.5 CONVERSION FROM HISTOGRAMS TO CODE EDGE TRANSFER CURVES 457 12.2.6 ACCURACY LIMITATIONS OF HISTOGRAM TESTING 460 12.2.7 RISING RAMPS VERSUS FALLING RAMPS 461 12.2.8 SINUSOIDAL HISTOGRAM METHOD 462 12.3 DC TESTS AND TRANSFER CURVE TESTS 467 12.3.1 DC GAIN AND OFFSET 467 12.3.2 MLANDDNL 468 12.3.3 MONOTONICITY AND MISSING CODES 469 12.4 DYNAMIC ADC TESTS 470 12.4.1 CONVERSION TIME, RECOVERY TIME, AND SAMPLING FREQUENCY 470 12.4.2 APERTURE JITTER 472 12.4.3 SPARKLING 472 CONTENTS XIII 12.5 ADC ARCHITECTURES 473 12.5.1 SUCCESSIVE APPROXIMATION ARCHITECTURES 473 12.5.2 INTEGRATING ADCS (DUAL-SLOPE AND SINGLE-SLOPE) 474 12.5.3 FLASH ADCS 475 12.5.4 SEMIFLASH ADCS 476 12.5.5 PDM (SIGMA-DELTA) ADCS 477 12.6 TESTS FOR COMMON ADC APPLICATIONS 479 12.6.1 DC MEASUREMENTS 479 12.6.2 AUDIO DIGITIZATION 479 12.6.3 DATA TRANSMISSION 479 12.6.4 VIDEO DIGITIZATION 480 12.7 SUMMARY 480 CHAPTER 13: DIB DESIGN 13.1 DIB BASICS 483 13.1.1 PURPOSE OF A DEVICE INTERFACE BOARD 483 13.1.2 DIB CONFIGURATIONS 484 13.1.3 IMPORTANCE OF GOOD DIB DESIGN 486 13.2 PRINTED CIRCUIT BOARDS 486 13.2.1 PROTOTYPE DIBS VERSUS PCB DIBS 486 13.2.2 PCB CAD TOOLS 487 13.2.3 MULTILAYER PCBS 488 13.2.4 PCB MATERIALS 489 13.3 DIB TRACES, SHIELDS, AND GUARDS 490 13.3.1 TRACE PARASITICS 490 13.3.2 TRACE RESISTANCE 490 13.3.3 TRACE INDUCTANCE 491 13.3.4 TRACE CAPACITANCE 496 13.3.5 SHIELDING 502 13.3.6 DRIVEN GUARDS 503 13.4 TRANSMISSION LINES 504 13.4.1 LUMPED-AND DISTRIBUTED-ELEMENT MODELS 504 13.4.2 TRANSMISSION LINE TERMINATION 508 13.4.3 PARASITIC LUMPED ELEMENTS 514 13.5 GROUNDING AND POWER DISTRIBUTION 514 13.5.1 GROUNDING 514 13.5.2 POWER DISTRIBUTION 516 13.5.3 POWER AND GROUND PLANES 517 13.5.4 GROUND LOOPS 518 13.6 DIB COMPONENTS 519 13.6.1 DUT SOCKETS AND CONTACTOR ASSEMBLIES 519 13.6.2 CONTACT PADS, POGO PINS, AND SOCKET PINS 520 13.6.3 ELECTROMECHANICAL RELAYS 521 13.6.4 SOCKET PINS 524 13.6.5 RESISTORS 525 13.6.6 CAPACITORS 526 13.6.7 INDUCTORS AND FERRITE BEADS 528 13.6.8 TRANSFORMERS AND POWER SPLITTERS 528 CONTENTS 13.7 COMMON DIB CIRCUITS 530 13.7.1 LOCAL RELAY CONNECTIONS 530 13.7.2 RELAY MULTIPLEXERS 532 13.7.3 SELECTABLE LOADS 533 13.7.4 ANALOG BUFFERS (VOLTAGE FOLLOWERS) 533 13.7.5 INSTRUMENTATION AMPLIFIERS 534 13.7.6 V M I D REFERENCE ADDER 535 13.7.7 CURRENT-TO-VOLTAGE AND VOLTAGE-TO-CURRENT CONVERSIONS 536 13.7.8 POWER SUPPLY RIPPLE CIRCUITS 536 13.8 COMMON DIB MISTAKES 540 13.8.1 POOR POWER SUPPLY AND GROUND LAYOUT 540 13.8.2 CROSSTALK 541 13.8.3 TRANSMISSION LINE DISCONTINUITIES 541 13.8.4 RESISTIVE DROPS IN CIRCUIT TRACES 541 13.8.5 TESTER INSTRUMENT PARASITICS 541 13.8.6 OSCILLATIONS IN ACTIVE CIRCUITS 542 13.8.7 POOR DIB COMPONENT PLACEMENT AND PCB LAYOUT 542 13.9 SUMMARY 543 APPENDIX A.13.1 543 CHAPTER 14: DESIGN FOR TEST (DFT) 14.1 OVERVIEW 549 14.1.1 WHAT IS DFT? 549 14.1.2 BUILT-IN SELF-TEST 550 14.1.3 DIFFERENCES BETWEEN DIGITAL DFT AND ANALOG DFT 550 14.1.4 WHY SHOULD WE USE DFT? 551 14.2 ADVANTAGES OF DFT 551 14.2.1 LOWER COST OF TEST 551 14.2.2 INCREASED FAULT COVERAGE AND IMPROVED PROCESS CONTROL 553 14.2.3 DIAGNOSTICS AND CHARACTERIZATION 553 14.2.4 EASE OF TEST PROGRAM DEVELOPMENT 554 14.2.5 SYSTEM-LEVEL DIAGNOSTICS 555 14.2.6 ECONOMICS OF DFT 555 14.3 DIGITAL SCAN 556 14.3.1 SCAN BASICS 556 14.3.2 IEEE STD. 1149.1 STANDARD TEST ACCESS PORT AND BOUNDARY SCAN 557 14.3.3 FULL SCAN AND PARTIAL SCAN 559 14.4 DIGITAL BIST 562 14.4.1 PSEUDORANDOM BILBO CIRCUITS 562 14.4.2 MEMORY BIST 563 14.4.3 MICROCODE BIST 564 14.5 DIGITAL DFT FOR MIXED-SIGNAL CIRCUITS 565 14.5.1 PARTITIONING 565 14.5.2 DIGITAL RESETS AND PRESETS 566 14.5.3 DEVICE-DRIVEN TIMING 567 14.5.4 LENGTHY PREAMBLES 569 14.6 MIXED-SIGNAL BOUNDARY SCAN AND BIST 569 14.6.1 MIXED-SIGNAL BOUNDARY SCAN (IEEE STD. 1149.4) 569 CONTENTS XV 14.6.2 ANALOG AND MIXED-SIGNAL BIST 571 14.7 AD HOC MIXED-SIGNAL DFT 573 14.7.1 COMMON CONCEPTS 573 14.7.2 ACCESSIBILITY OF ANALOG SIGNALS 573 14.7.3 ANALOG TEST BUSES, T-SWITCHES, AND BYPASS MODES 575 14.7.4 SEPARATION OF ANALOG AND DIGITAL BLOCKS 577 14.7.5 LOOPBACK MODES 579 14.7.6 PRECHARGING CIRCUITS AND AC COUPLING SHORTS 580 14.7.7 ON-CHIP SAMPLING CIRCUITS 581 14.7.8 PLL TESTABILITY CIRCUITS 583 14.7.9 DAC AND ADC CONVERTERS 584 14.7.10 OSCILLATION BIST 585 14.7.11 PHYSICAL TEST PADS 585 14.8 SUBTLE FORMS OF ANALOG DFT 585 14.8.1 ROBUST CIRCUITS 585 14.8.2 DESIGN MARGIN AS DFT 586 14.8.3 AVOIDING OVERSPECIFICATION 586 14.8.4 PREDICTABILITY OF FAILURE MECHANISMS 586 14.8.5 CONVERSION OF ANALOG FUNCTIONS TO DIGITAL 587 14.8.6 REDUCED TESTER PERFORMANCE REQUIREMENTS 587 14.8.7 AVOIDANCE OF TRIM REQUIREMENTS 587 14.9 I DDQ 587 14.9.1 DIGITAL I DDQ 587 14.9.2 ANALOG AND MIXED-SIGNAL I DDQ 588 14.10 SUMMARY 589 APPENDIX A.14.1 589 CHAPTER 15: DATA ANALYSIS 15.1 INTRODUCTION TO DATA ANALYSIS 597 15.1.1 THE ROLE OF DATA ANALYSIS IN TEST AND PRODUCT ENGINEERING 597 15.1.2 VISUALIZING TEST RESULTS 597 15.2 DATA VISUALIZATION TOOLS 598 15.2.1 DATALOGS (DATA LISTS) 598 15.2.2 LOT SUMMARIES 599 15.2.3 WAFER MAPS 600 15.2.4 SHMOO PLOTS 601 15.2.5 HISTOGRAMS 604 15.3 STATISTICAL ANALYSIS 606 15.3.1 MEAN (AVERAGE) AND STANDARD DEVIATION (VARIANCE) 606 15.3.2 PROBABILITES AND PROBABILITY DENSITY FUNCTIONS 607 15.3.3 THE STANDARD GAUSSIAN CUMULATIVE DISTRIBUTION FUNCTION (Z) 611 15.3.4 NON-GAUSSIAN DISTRIBUTIONS 615 15.3.5 GUARDBANDING AND GAUSSIAN STATISTICS 618 15.3.6 EFFECTS OF MEASUREMENT VARIABILITY ON TEST YIELD 620 15.3.7 EFFECTS OF REPRODUCIBILTY AND PROCESS VARIATION ON YIELD 623 15.4 STATISTICAL PROCESS CONTROL 627 15.4.1 GOALS OF SPC 627 15.4.2 SIX-SIGMA QUALITY 628 XVI CONTENTS 15.4.3 PROCESS CAPABILITY, C P , AND C PK 628 15.4.4 GAUGE REPEATABILITY AND REPRODUCIBILITY 630 15.4.5 PARETO CHARTS 631 15.4.6 SCATTER PLOTS 631 15.4.7 CONTROL CHARTS 633 15.5 SUMMARY 634 CHAPTER 16: TEST ECONOMICS 16.1 PROFITABILITY FACTORS 641 16.1.1 WHAT IS MEANT BY TEST ECONOMICS? 641 16.1.2 TIME TO MARKET 641 16.1.3 TESTING COSTS 642 16.1.4 YIELD ENHANCEMENT 642 16.2 DIRECT TESTING COSTS 643 16.2.1 COST MODELS 643 16.2.2 COST OF TEST VERSUS COST OF TESTER 643 16.2.3 THROUGHPUT 645 16.3 DEBUGGING SKILLS 649 16.3.1 SOURCES OF ERROR 649 16.3.2 THE SCIENTIFIC METHOD 649 16.3.3 PRACTICAL DEBUGGING SKILLS 651 16.3.4 IMPORTANCE OF BENCH INSTRUMENTATION 652 16.3.5 TEST PROGRAM STRUCTURE 652 16.3.6 COMMON BUGS AND TECHNIQUES TO FIND THEM 653 16.4 EMERGING TRENDS 655 16.4.1 TEST LANGUAGE STANDARDS 655 16.4.2 TEST SIMULATION 656 16.4.3 NONCOHERENT SAMPLING 658 16.4.4 BUILT-IN SELF-TEST 658 16.4.5 DEFECT-ORIENTED TESTING 658 16.5 SUMMARY 659 ANSWERS TO SELECTED PROBLEMS 663 INDEX 677
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spelling	Burns, Mark Verfasser aut An introduction to mixed signal IC test and measurement Mark Burns ; Gordon W. Roberts An introduction to mixed-signal IC test and measurement New York, NY [u.a.] Oxford Univ. Press 2001 XX, 684 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Oxford series in electrical and computer engineering Integrated circuits -- Testing Mixed signal circuits -- Testing Testen (DE-588)4367264-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Testen (DE-588)4367264-4 s DE-604 Roberts, Gordon W. Verfasser aut text/html http://catdir.loc.gov/catdir/enhancements/fy0610/00042770-d.html Publisher description text/html http://catdir.loc.gov/catdir/enhancements/fy0610/00042770-t.html Table of contents only GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009501296&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Burns, Mark Roberts, Gordon W. An introduction to mixed signal IC test and measurement Integrated circuits -- Testing Mixed signal circuits -- Testing Testen (DE-588)4367264-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd
subject_GND	(DE-588)4367264-4 (DE-588)4027242-4
title	An introduction to mixed signal IC test and measurement
title_alt	An introduction to mixed-signal IC test and measurement
title_auth	An introduction to mixed signal IC test and measurement
title_exact_search	An introduction to mixed signal IC test and measurement
title_full	An introduction to mixed signal IC test and measurement Mark Burns ; Gordon W. Roberts
title_fullStr	An introduction to mixed signal IC test and measurement Mark Burns ; Gordon W. Roberts
title_full_unstemmed	An introduction to mixed signal IC test and measurement Mark Burns ; Gordon W. Roberts
title_short	An introduction to mixed signal IC test and measurement
title_sort	an introduction to mixed signal ic test and measurement
topic	Integrated circuits -- Testing Mixed signal circuits -- Testing Testen (DE-588)4367264-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd
topic_facet	Integrated circuits -- Testing Mixed signal circuits -- Testing Testen Integrierte Schaltung
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