Proceedings 2001: GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Assoc. for Computing Machinery
2001
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XII, 152 S. |
| ISBN: | 1581133510 |
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| 245 | 1 | 0 | |a Proceedings 2001 |b GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 |c Great Lakes Symposium on VLSI |
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Datensatz im Suchindex
| _version_ | 1804128709144215552 |
|---|---|
| adam_text | Contents
Welcome
.................................................................................................................
viii
Symposium Organization
.......................................................................................ix
Reviewers
.................................................................................................................xi
Dinnerflnvited Speaker
.........................................................................................xii
1.
Test and Verification I
Session Chair: Patrick H. Madden (State University of New York, Binghamton)
1.1
Practical Approaches to the Verification of a Telecom Megacell using
FormalCheck
.........................................................................................................1
Leila Barakatain, Sofiene Tahar
(Concordia
University, Canada), Jean
Lamarche, Jean-Marc Gendreau (PMC Sierra, Inc., Canada)
1.2
A Novel Reseeding Technique for Accumulator-based Test Pattern
Generation
.............................................................................................................7
X. Kavousianos, D. Bakalis, D. Nikolos (University ofPatras, Greece)
1.3
ITEM: An Iterative Improvement Test Generation Procedure for
Synchronous Sequential Circuits
........................................................................13
Irith Pomeranz (Purdue University), Sudhakar M. Reddy (University of Iowa)
2.
High Level Synthesis and Physical Synthesis
Session Chair: Hannah H. Yang (Intel Corporation)
2.1
Solving Large Scale Assignment Problems in High-Level Synthesis by
Approximate Quadratic Programming
................................................................19
Florin Balasa (University of Illinois, Chicago), Werner Geurts (Target
Compiler Technologies, Belgium),
Francky
Catthoor, Hugo
De Man
(Interuniversity Microelectronics Center (IMEC), and
Katholieke Universiteit
Leuven,
Belgium)
2.2
Layout Aware Retiming
.....................................................................................25
A. Ranjan, A. Srivastava, V. Karnam, M. Sarrafzadeh (Northwestern
University)
III
2.3 Optimal
Partitioning and Balanced Scheduling with Maximal Overlap of Data
Footprints
............................................................................................................31
Zhong Wang (University of Notre Dame), Edwin H.-M.
Sha,
and Yuke Wang
(University of Texas, Dallas)
3.
Challenges in Advanced VLSI Design
Session Chair: Kaushik Roy (Purdue University)
3.1
SOI For Asynchronous Dynamic Circuits
.........................................................37
R. V. Joshi, W. Hwang, C. T. Chuang (IBM T. J. Watson Research Center)
3.2
Leakage Control and Tolerance Challenges for Sub-O.lum Microprocessor
Circuits
................................................................................................................43
Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar (Intel Corporation)
3.3
Challenges in Integrated CMOS Transceivers for Short Distance Wireless
......45
Khurram Muhammad, Robert B. Staszewski (Texas Instruments),
Poras
T.
Balsara
(University of Texas at Dallas)
4.
Physical Design
Session Chair: John Lillis (University of Illinois, Chicago)
4.1
An Accurate Evaluation of Routing Density for Symmetrical FPGAs
..............51
Nak- Woong Eum, Taewhan Kim, Chong-Min Kyung (KAIST, Korea)
4.2
Preferred Direction
Steiner
Trees
.......................................................................56
Mehmet
Can Yildiz and Patrick H. Madden (State University of New York,
Binghamton)
4.3
Faster and More Accurate Wiring Evaluation in Interconnect-Centric
Floorplanning (S)
................................................................................................62
Hung-Ming Chen, D. F. Wong (University of Texas, Austin), Wai-Kei
Mak
(University of South Florida), and Hannah H. Yang (Intel Corporation)
4.4
Global Objectives for Standard Cell Placement (S)
...........................................68
Mehmet
Can Yildiz and Patrick H. Madden (State University of New York,
Binghamton)
IV
5.
Architectures and Cache
Session Chair: Ram Krishnamurthy (Intel Corporation)
5.1
A Circuit
Level Implementation of an Adaptive
Issue Queue for Power-
Aware
Microprocessors..................................................................................................
73
Alper
Buyuktosunoglu, Stanley
Schuster,
David
Brooks, Pradip
Bose,
Peter
Cook (IBM
T. J.
Watson Research Center), David
H
.
Albonesi (University of
Rochester)
5.2
A CORDIC Based Array Architecture for Complex Discrete Wavelet
Transform
............................................................................................................79
Bipul Das and
Swapna Baner
jee
(Indian Institute of Technology, Kharagpur,
India)
5.3
A VLSI Wrapped Wave Front Arbiter for Crossbar Switches (S)
.....................85
Jose G. Delgado-Frias, Girish B. Ratanpal (University of Virginia)
5.4
Effective Algorithms for Cache-Level Compression (S)
...................................89
Edward
Ahn, Seung-Moon
Yoo (University of Illinois, Urbana-Champaign),
Sung-Mo (Steve) Kang (University of California, Santa Cruz)
6.
Test and Verification II
Session Chair: Sofiene Tahar
(Concordia
University, Canada)
6.1
2-Level LFSR Scheme with Asynchronous Test Pattern Transfer for Low Cost
and High Efficiency Built-In-Self-Test
................................................................93
Seung-Moon Yoo, Seong-Ook Jung (University of Illinois,
Urbana-Champaign), Sung-Mo (Steve) Kang (University of California, Santa
Cruz)
6.2
Rarity Based Guided State Space Search
...........................................................97
Malay K. Ganai, Adnan Aziz (University of Texas, Austin)
6.3
Who are the Alternative Wires in Your Neighborhood
....................................103
Chih-Wei (Jim) Chang, and M. Marek-Sadowska (University of California,
Santa Barbara)
7.
Power
and Interconnect Modeling
Session Chair: Khurram Muhammad (Texas Instruments)
7.1
Hierarchical Model Order Reduction for Signal-Integrity Driven Interconnect
Synthesis
...........................................................................................................109
Yu-Min Lee and Charlie Chung-Ping Chen (University of Wisconsin, Madison)
7.2
An Efficient Model for Frequency-Dependent On-Chip Inductance
...............115
Min Xu
and Lei He (University of Wisconsin, Madison)
7.3
Models for Power Consumption and Power Grid Noise Due to Datapath
Transition Activity
.............................................................................................121
Lijun
Gao
and Keshab K. Parhi (University of Minnesota)
8.
Advances in Nanotechnology
Session Chair: David B. Janes (Purdue University)
8.1
Electronic Devices, Structures and Transport in Carbon based Materials:
Molecular Electronics and Quantum Computing
..............................................127
Deepak Srivastava (NASA Ames Research Center)
8.2
Single Molecule Electronics
............................................................................128
Mark Hersam (Northwestern University)
8.3
Self-Aligned Dual Gate MOSFETS and
3-D
CMOS
.......................................129
John
Dentón
(Purdue University)
9.
Circuit Design
Session Chair: Zhanping Chen (Intel Corporation)
9.1
Transistor Sizing for Reliable Domino Logic Design in Dual Threshold
Voltage Technologies
........................................................................................133
Seong-Ook Jung, Ki-WookKim (University of Illinois, Urbana-Champaign),
Sung-Mo (Steve) Kang (University of California, Santa Cruz)
9.2
Practical Low-Cost CPL Implementations of Threshold Logic Functions
......139
J.M.
Quintana,
MJ.
Avedillo and
E.
Rodríguez-Villegas (Instituto de
Microlectronica de
Sevilla
(IMSE-CNM),
Spain)
VI
9.3
A High Performance RNS Multiply-Accumulate Unit (S)
..............................145
A. P. Preethy (Nanyang Technological University, Singapore),
Damu
Radhakrishnan (State University of New York, New Paltz), Amos Omondi
(Nanyang Technological University, Singapore)
9.4
A Fast Hybrid Carry-Lookahead/Carry-Select Adder Design (S)
...................149
Ohsang Kwon, Earl
E
.
Swartzlander (University of Texas, Austin), Kevin
Nowka (IBM Austin Research Lab)
vu
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| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:53:33Z |
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| language | English |
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| spelling | Great Lakes Symposium on VLSI 11 2001 West Lafayette, Ind. Verfasser (DE-588)10028275-1 aut Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 Great Lakes Symposium on VLSI New York, NY Assoc. for Computing Machinery 2001 XII, 152 S. txt rdacontent n rdamedia nc rdacarrier Circuits intégrés à très grande échelle - Congrès ram VLSI inriac circuit intégré inriac circuit électronique inriac Computer-aided design Congresses Integrated circuits Very large scale integration Design and construction Congresses VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 West Lafayette Ind. gnd-content VLSI (DE-588)4117388-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009489931&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 Circuits intégrés à très grande échelle - Congrès ram VLSI inriac circuit intégré inriac circuit électronique inriac Computer-aided design Congresses Integrated circuits Very large scale integration Design and construction Congresses VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)1071861417 |
| title | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 |
| title_auth | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 |
| title_exact_search | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 |
| title_full | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 Great Lakes Symposium on VLSI |
| title_fullStr | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 Great Lakes Symposium on VLSI |
| title_full_unstemmed | Proceedings 2001 GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 Great Lakes Symposium on VLSI |
| title_short | Proceedings 2001 |
| title_sort | proceedings 2001 glsvlsi 2001 purdue university west lafayette indiana march 22 23 2001 |
| title_sub | GLSVLSI 2001 ; Purdue University, West Lafayette, Indiana, March 22 - 23, 2001 |
| topic | Circuits intégrés à très grande échelle - Congrès ram VLSI inriac circuit intégré inriac circuit électronique inriac Computer-aided design Congresses Integrated circuits Very large scale integration Design and construction Congresses VLSI (DE-588)4117388-0 gnd |
| topic_facet | Circuits intégrés à très grande échelle - Congrès VLSI circuit intégré circuit électronique Computer-aided design Congresses Integrated circuits Very large scale integration Design and construction Congresses Konferenzschrift 2001 West Lafayette Ind. |
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