Proceedings of ISPD '01: 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
ACM Press
2001
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | X, 245 S. Ill., graph. Darst. |
| ISBN: | 1581133472 |
Internformat
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| 245 | 1 | 0 | |a Proceedings of ISPD '01 |b 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
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Datensatz im Suchindex
| _version_ | 1804128693363146752 |
|---|---|
| adam_text | Table
of Contents
Symposium Organization List
....................................................................................................
v i
Keynote Address
........................................................................................................................
ix x
Session
1:
Panel: Differences in ASIC, COT and Processor Design
1-2
Organizer and Chair: M. Sarrafzadeh (University of California, Los Angeles)
Panelists:
N.
Nettleton (Sun), W. Roethig (NEC), D. Hill (Synopsys)
Session
2:
Routing the Global Interconnect Problem
Chair: H. Zhou (Synopsys)
Buffered
Steiner
Trees for Difficult Instances
.................................................................4
C. J.
Alpert (IBM),
M.
Hrkic (University of Illinois, Chicago), J.
Hu (IBM),
A. B. Kahng (University of California, San Diego), J.
Ullis
(University of Illinois, Chicago),
B. Liu (University of California, San Diego), S. T. Quay (IBM),
S. S. Sapatnekar (University of Minnesota), A. J. Sullivan (IBM), and P. Villarrubia (IBM)
An Exact Algorithm for Coupling-Free Routing
............................................................10
R.
Kastner,
E.
Bozorgzadeh, and M. Sarrafzadeh (University of California, Los Angeles)
RC(L) Interconnect Sizing with Second Order Considerations
via Posynomial Programming
.........................................................................................16
T. Lin and L. T. Pileggi (Carnegie Mellon University)
Session
3:
Placement
Chair:
S. Raje
(Monterey Design Systems)
A Performance-Driven Standard-Cell Placer Based on a Modified
Force-Directed Algorithm
................................................................................................24
Y.-C.
Chou
and Y.-L. Lin (National
Tsing Hua
University)
Reporting of Standard Cell Placement Results
.............................................................30
P. H. Madden (State University of New York, Binghamton)
Session
4:
Manufacturing and Design Variability, Needs and Solutions
Chair: A. B. Kahng (University of California, San Diego)
Application of Automated Design Migration to Alternating Phase Shift
Mask Design (Invited)
......................................................................................................38
F.-L.
Heng,
L.
Liebmann,
and J.
Lund
(IBM)
Reticle Enhancement Technology Trends: Resources and Manufacturability
Implications for the Implementation of Physical Designs (Invited)
.............................45
W. Grobman, R. Boone,
С
Philbin,
and
R.
Jarvis (Motorola SPS)
Impact
of RET on Physical Layouts (Invited)
.................................................................52
F. M.
Schellenberg
(Mentor Graphics) and L. Capodieci (ASML MaskTools)
Session
5:
Issues in the Design of Supply Networks
Chair: D. Kirkpatrick (Intel)
Power Trends and Issues in Physical Design (Invited)
................................................59
S. Kumar (Intel)
Design of Robust Global Power and Ground Networks
...............................................60
S. Boyd (Stanford University), L. Vandenberghe (University of California, Los Angeles)
A. El
Gamai
and S. Yun (Stanford University),
Decoupling Capacitance Allocation for Power Supply Noise Suppression
...............66
S. Zhao, K. Roy, and C.-K. Koh (Purdue University)
Session
6:
Fundamental CAD Algorithms
Chair: L. Scheffer (Cadence)
Overview of Continuous Optimization Advances and Applications
to Circuit Tuning (Invited)
................................................................................................74
A. R. Conn and
С
Visweswariah (IBM)
Design and Analysis of Physical Design Algorithms (Invited)
....................................82
M. Sarrafzadeh, E. Bozorgzadeh, R.
Kastner,
and A. Srivastava
(University of California, Los Angeles)
Session
7:
Multi-GHz Interconnect Effects in Microprocessors
Chair:
D. F.
Wong (University of Texas, Austin)
Multi-GHz Interconnect Effects in Microprocessors (Invited)
......................................93
P. J.
Restie,
A. E. Ruehli, and S. G. Walker (IBM)
Session
8:
Poster Papers
Chair: C.-K. Koh (Purdue University)
Min-Cut Partitioning with Functional Replication for Technology
Mapped Circuits using Minimum Area Overhead
.......................................................100
W.-K.
Мак
(University of South Florida)
Maximum Current Estimation Considering Power Gating
106
F. Li and
L
He (University of Wisconsin)
Estimating Routing Congestion using Probabilistic Analysis
112
J. Lou, S. Krishnamoorthy, and
H. S.
Sheng (Synopsys)
Dummy Feature Placement
for Chemical-Mechanical Polishing Uniformity
in a Shallow Trench Isolation Process
.........................................................................118
fl. Tian
(University of Texas, Austin
&
Motorola Inc.),
X. Tang and D. F. Wong (University of Texas, Austin)
Slicing Floorplan Design with Boundary-Constrained Modules
...............................124
E.-C. Liu, M.S. Lin (Chung Yuan Christian University), J. Lai (Tatung Corp.),
and T.-C. Wang (Texas A&M University)
A Regularity-Driven Fast Gridless Detailed Router for High Frequency
Datapath Designs
...........................................................................................................130
S. Das (Intel Corporation) and S. P. Khatri (University of Colorado)
Session
9:
Floorplanning
Chair:
С
N.
Chu
(Iowa State University)
Aftermath of Floorplan Representations
138
B. Yao, H. Chen, C.-K. Cheng, and Ft. Graham (University of California, San Diego)
Consistent Floorplanning with Super Hierarchical Constraints
................................144
S. Nakatake,
Y. Kubo,
and Y. Kajitani (The University of Kitakyushu)
ECBL: An Extended Corner Block List with Solution Space
including Optimum Placement
......................................................................................150
S. Zhou, S. Dong, X. Hong, Y.
Cai (Tsinghua
University), C.-K. Cheng
(University of California at San Diego), and J. Gu (Science
&
Technology University of Hong Kong)
Rectilinear Block Packing Using
О
-tree
Representation
............................................156
У.
Pang, K. Lampaert (Mindspeed Technologies), C.-K. Cheng
(University of California at San Diego), and W. Xie (Hewlett-Packard Research Laboratories)
Session
10:
Predicting and Analyzing Layout Characteristics
Chair:
C. J.
Alpert (IBM)
Congestion Estimation During Top-down Placement
................................................164
X. Yang. R.
Kastner,
and M. Sarrafzadeh (University of California, Los Angeles)
Interconnect Characteristics of 2.5-D System Integration Scheme
...........................171
Y. Deng and W. P. Maly (Carnegie Mellon University)
Session
11 :
Design Closure
Chair: M. Pedram (University of Southern California)
Hierarchical Physical Design Methodology for Multi-Million
Gate Chips (Invited)
........................................................................................................179
W.-J. Dai (Silicon Perspective)
Overcoming Wireload Model Uncertainty During Physical Design (Invited)
............182
P. Gopalakrishnan, A. Odabasioglu, L.
Fileggi,
and
S. Raje
(Monterey Design Systems)
Session 12: New Solutions
to Traditional
Problems
Chair:
R. H. J. M.
Otten (Eindhoven)
A Minimum Cost Path Search Algorithm Through Tile Obstacles
...........................192
Z
Xing and R.
Kao
(Sun Microsystems Laboratories)
An Exact Algorithm for Solving Difficult Detailed Routing Problems
.......................198
K.
Sulimmá
and W. Kunz
(J.
W.
Goethe-Universität
Frankfurt)
Boosters for Driving Long On-chip Interconnects: Design Issues,
Interconnect Synthesis and Comparison with Repeaters
..........................................204
A. Nalamalpu (Intel) and W. Burleson (University of Massachusetts)
Session
13:
FPGA PD in
DSM
VLSI
Chair: D. Hill (Synopsys)
Physical Design for FPGAs (Invited)
............................................................................214
R. Jayaraman (Xilinx)
A Comparative Study of Two Boolean Formulations of FPGA Detailed
Routing Constraints
.......................................................................................................222
G.-J. Nam, F. Aloul,
K. Sakallah
(University of Michigan),
and R.
Rutenbar
(Carnegie Mellon University)
Session
14:
Hot Ideas in Thermal Analysis and Optimization
Chair: P. Groeneveld (Magma)
Analysis and Optimization of Thermal Issues
in High Performance VLSI (Invited)
..............................................................................230
K. Banerjee (Stanford University), M. Pedram and A. H. Ajami (University of Southern California)
Thermal-ADI: a Linear-Time Chip-Level Dynamic Thermal Simulation
Algorithm Based on Alternating-Direction-lmplicit (ADI) Method
.............................238
T.-Y. Wang and
С. С.-Р.
Chen (University of Wisconsin, Madison)
Author Index
...............................................................................................................................245
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| spelling | International Symposium on Physical Design 5 2001 Sonoma, Calif. Verfasser (DE-588)10025807-4 aut Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 New York, NY ACM Press 2001 X, 245 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 Sonoma Calif. gnd-content CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009479338&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| title_auth | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| title_exact_search | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| title_full | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| title_fullStr | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| title_full_unstemmed | Proceedings of ISPD '01 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| title_short | Proceedings of ISPD '01 |
| title_sort | proceedings of ispd 01 2001 international symposium on physical design sonoma california usa april 1 1 4 2001 |
| title_sub | 2001 International Symposium on Physical Design, Sonoma, California, USA, April 1 -1 4, 2001 |
| topic | CAD (DE-588)4069794-0 gnd |
| topic_facet | CAD Konferenzschrift 2001 Sonoma Calif. |
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