FPGA '01: ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Assoc. for Computing Machinery
2001
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VII, 231 S. Ill., graph. Darst. |
| ISBN: | 1581133413 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1820868243264372736 |
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| adam_text |
Table
of
Contents
Session
1 :
Placement
and Routing
Chair:
Carl Ebeling, University of
Washington
Timing-Driven
Placement
for Hierarchical
Programmable
Logic Devices
.
з
M. Hutton, K.
Adibsamii, and A. Leaver
(Altera
Corporation)
LRoute: A
Delay
Minimal Router
for Hierarchical CPLDs
.12
K. K. Lee (Synopsys, Inc.) and M. D. F.
Wong (University of
Texas
at Austin)
A Crosstalk-Aware Timing-Driven Router for FPGAs
.21
S. J. E. Wilton (University of British Columbia)
Runtime and Quality Tradeoffs in FPGA Placement and Routing
.29
C. Mulpuri and S. Hauck (University of Washington)
Session
2:
Technology Mapping
Chair: Steven Wilton, University of British Columbia
Performance-Driven Mapping for CPLD Architectures
.39
D. Chen, J. Cong, M. D. Ercegovac, and Z. Huang (University of California, Los Angeles)
Simultaneous Logic Decomposition with Technology Mapping
in FPGA Designs
.48
G. Chen and J. Cong (University of California, Los Angeles)
Session
3:
Routing Architectures
Chair: Tom Kean, Algotronix
Using Sparse Crossbars within
LUT
Clusters
59
G. Lemieux and D. Lewis (University of Toronto)
Detailed Routing Architectures for Embedded Programmable
Logic IP Cores
.69
P. Hallschmid and S. J. E. Wilton (University of British Columbia)
Mixing Buffers and Pass Transistors in FPGA Routing Architectures
75
M. Sheng and J. Rose (University of Toronto)
Session 4: Applications
Chair:
Ray Andraka, Andraka Consulting
Reprogrammable
Network Packet Processing
on the Field
Programmable Port Extender (FPX)
.87
J. W.
Lockwood, N.
Naufel, J. S. Turner, and D. E. Taylor (Washington University)
Fast Implementations of Secret-Key Block Ciphers Using
Mixed Inner- and Outer-Round Pipelining
.94
P. Chodowiec, P. Khuon, and K.
Gaj
(George Mason University)
Algorithmic Transformations in the Implementation of K-means
Clustering on
Reconfigurable
Hardware
.
юз
M.
Estlick,
M.
Leeser (Northeastern University), J. J. Szymanski,
and J. Theiler (Los Alamos National Laboratory)
Panel: Is Marriage in the Cards for Programmable Logic,
Microprocessors and ASICs?
.111
Moderator: S. Kaptanoglu (Adaptive Silicon)
Panalists: J. East (Actel), T. Garverick (Adaptive Silicon), S. Hauck (University of Washington),
D. Papworth (Intel), D.
Tavana
(Triscend), S. Trimberger (Xilinx), and R. Vasishta (LSI Logic)
Session
5:
Reconfigurable
Computing
Chair: Steve Trimberger, Xilinx
Attacking the Semantic Gap Between Application Programming
Languages and Configurable Hardware
.115
G. Snider, B. Shackleford, and R. J. Carter (Hewlett-Packard Laboratories)
Matching and Searching Analysis for Parallel Hardware
Implementation on FPGAs
.125
P. Moisset, P. Diniz, and J. Park (University of Southern California/Information Sciences Institute)
Evaluation of the Streams
-С
C-to-FPGA Compiler: An Applications
Perspective
.134
J.
Frigo, M.
Gokhale (Los Alamos National Laboratory), and D. Lavenier (IRISA-CNRS)
The Effect of
Reconfigurable
Units in Superscalar Processors
.141
J. E. Carrillo E. and P. Chow (University of Toronto)
Session 6:
Pipelined
Routing
Architectures
Chair: Andre DeHon,
Cal
Tech
Interconnect Pipelining in a Throughput-Intensive FPGA Architecture
.153
A. Singh, A. Mukherjee, and M. Marek-Sadowska (University of California. Santa Barbara)
The Case for Registered Routing Switches in Field Programmable
Gate Arrays
.
161
D. P. Singh and S. D. Brown (University of Toronto)
Session
7:
Issues in FPGA-Based Systems
Chair: Chuck Stroud, University of North Carolina-Charlotte
Configuration Compression for FPGA-based Embedded Systems
173
A. Dandalis and V. K. Prasanna (University of Southern California)
A Memory Coherence Technique for Online Transient Error
Recovery of FPGA Configurations
.
18З
W.-J. Huang and E. J. McCluskey (Stanford University)
Run-Time Defect Tolerance using JBits
.193
P. Sundararajan and S. A. Guccione (Xilinx, Inc.
)
Session
8:
Applications in Image/Video Compression
Chair: Miriam Leeser, Northeastern University
A Pipelined Architecture for Partitioned DWT Based Lossy Image
Compression using FPGA's
.201
J.
Ritter
and P. Molitor (Martin-Luther-University Halle-Wittenberg)
An FPGA-Based Video Compressor for H.263 Compatible
Bit Streams
.207
G. Lienhart, R.
Männer
(University of Mannheim). R. Lay and K. H. Noffz (Silicon Software GmbH)
FPGA Implementation of a Novel, Fast Motion Estimation Algorithm
for Real-Time Video Compression
21
з
S.
Ramachandran and S. Srinivasan (Indian Institute of Technology. Madras/
Poster Abstracts
.221
(Alphabetically by title)
Author Index
.
--'i |
| any_adam_object | 1 |
| author_corporate | FPGA Monterey, Calif |
| author_corporate_role | aut |
| author_facet | FPGA Monterey, Calif |
| author_sort | FPGA Monterey, Calif |
| building | Verbundindex |
| bvnumber | BV013777978 |
| classification_rvk | SS 2001 |
| classification_tum | DAT 195f |
| ctrlnum | (OCoLC)632939693 (DE-599)BVBBV013777978 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| illustrated | Illustrated |
| indexdate | 2025-01-10T13:21:16Z |
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| isbn | 1581133413 |
| language | English |
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| physical | VII, 231 S. Ill., graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Assoc. for Computing Machinery |
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| spelling | FPGA 9 2001 Monterey, Calif. Verfasser (DE-588)10022620-6 aut FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA FPGA 2001 New York, NY Assoc. for Computing Machinery 2001 VII, 231 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Gate-Array-Bauelement (DE-588)4113666-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2001 Monterey Calif. gnd-content Gate-Array-Bauelement (DE-588)4113666-4 s DE-604 Association for Computing Machinery Special Interest Group on Design Automation Sonstige (DE-588)10620-3 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009418725&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA Gate-Array-Bauelement (DE-588)4113666-4 gnd |
| subject_GND | (DE-588)4113666-4 (DE-588)1071861417 |
| title | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| title_alt | FPGA 2001 |
| title_auth | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| title_exact_search | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| title_full | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| title_fullStr | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| title_full_unstemmed | FPGA '01 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| title_short | FPGA '01 |
| title_sort | fpga 01 acm sigda international symposium on field programmable gate arrays monterey california usa |
| title_sub | ACM SIGDA International Symposium on Field Programmable Gate Arrays ; Monterey, California, USA |
| topic | Gate-Array-Bauelement (DE-588)4113666-4 gnd |
| topic_facet | Gate-Array-Bauelement Konferenzschrift 2001 Monterey Calif. |
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