Proceedings: 10 - 13 December 2000, Monterey, California, USA
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. [u.a.]
IEEE Computer Soc.
2000
|
| Schriftenreihe: | Micro
33 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Einzelaufnahme eines Zeitrschr.-Bandes |
| Beschreibung: | XIV, 257 S. Ill., graph. Darst. |
| ISBN: | 076950924X 0769509266 |
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Datensatz im Suchindex
| _version_ | 1820868239159197696 |
|---|---|
| adam_text |
Table
of
Contents
33rd Annual International Symposium on
Microarchitecture
MICRO-33
Foreword
.ix
Committees
.xi
Reviewers
.xiii
Keynote Speakers
A Whole New Ballgame-Supercomputing on Two AA Batteries
.3
David Baker
BOPS Inc.
Breathing Life into a Paper Tiger
.5
Darrell Boggs
Intel
Defect Tolerant Molecular Electronics: Algorithms, Architectures, and Atoms
.7
Phil Keukes
Hewlett-Packard
Memory Hierarchy I
_
Session Chair:
Ronny Ronen,
Intel
Eager Writeback
—
A Technique for Improving Bandwidth Utilization
.11
H.-H. S. Lee, G. S. Tyson, and M. K.
F
ärrens
Silent Stores for Free
.22
K. M. Lepak and M. H.
Lipasu
A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer
Conflicts and Exploit Data Locality
.32
Z. Zhang, Z. Zhu, and X. Zhang
Predictor-Directed Stream Buffers
.42
T. Sherwood, S.
Sair,
and B.
Calder
Superscalar Architecture I
_
Session Chair: Gary Tyson, University of Michigan
On Pipelining Dynamic Instruction Scheduling Logic
.57
J. Stark, M. D. Brown, and Y.
N.
Patt
The Impact of Delay on the Design of Branch Predictors
.67
D.
A. Jiménez,
S.
W.
Keckler, and
C. Lin
Improving
ВТВ
Performance in the Presence of DLLs
.77
S. Vlaovic, E. S. Davidson, and G. S. Tyson
Efficient Checker Processor Design
.87
S. Chatterjee, C. Weaver, and T. Austin
Compilation
Session Chair: Carol Thompson, Hewlett-Packard
An Integrated Approach to Accelerate Data and Predicate
Computations in Hyperblocks
.101
A. Eichenberger, W.
Meleis,
and S.
Maradani
Accurate and Efficient Predicate Analysis with Binary Decision Diagrams
.112
J. W.
Sias,
W. W.
Hwu, and
D.
I. August
Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture
.124
J. Sanchez and A. Gonzalez
Accelerator Architecture
Session Chair: Tom
Conte,
North Carolina State University
Two-Level Hierarchical Register File Organization for VLIW Processors
.137
J.
Zalamea,
J.
Uosa, E.
Ayguadé,
and
M.
Valero
PipeRench Implementation of the Instruction Path Coprocessor
.147
Y. Chou,
P.
Pillai, H.
Schmit, andJ. P. Shen
Efficient Conditional Operations for Data-Parallel Architectures
.159
U. J. Kapasi, W. J. Dally, S. Rixner, P. R.
Mattson,
J. D. Owens, and B. Khailany
Flexible Hardware Acceleration for Multimedia Oriented Microprocessors
.171
F. Vermeulen,
L.
Nachtergaele,
F.
Catthoor,
D.
Verkest,
and
H. De
Man
Low-Power
Design
Session
Chair: Rajiv Gupta, University of Arizona
Very Low Power Pipelines Using Significance Compression
.181
R. Canal,
A. González,
and
J. E.
Smith
A Static Power Model for Architects
.191
J. A. Butts and G. S.
Sohi
A Framework for Dynamic Energy Efficiency and Temperature Management
.202
M. Huang, J. Renau, S.-M. Yoo, andJ.
Torrellas
Dynamic Zero Compression for Cache Energy Reduction
.214
L
Villa, M. Zhang, and K.
Asanović
Memory Hierarchy II
Session Chair: Mike Smith, Harvard University
Register Integration: A Simple and Efficient Implementation
of Squash Reuse
.223
A. Roth and G. S.
Sohi
The Store-Load Address Table and Speculative Register Promotion
.235
M. Postiff, D. Greene, and T. Mudge
vi
Memory
Hierarchy Reconfiguration for Energy and Performance in
General-Purpose Processor Architectures
.245
R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas
Frequent Value Compression in Data Caches
.258
J. Yang, Y. Zhang, and R. Gupta
Dynamic Translation and Multithreading
_
Session Chair: Kemal Ebcioglu, IBM
A Study of Slipstream Processors
.269
Z. Purser, K. Sundaramoorthy, and E.
Rotenberg
Relational Profiling: Enabling Thread-Level Parallelism
in Virtual Machines
.281
T.
Heil
and J. E. Smith
Calpa:
A Tool for Automating Selective Dynamic Compilation
.291
M. Mock, C. Chambers, and S. J. Eggers
Increasing the Size of Atomic Instruction Blocks Using Control
Flow Assertions
.303
5.
J.
Patel,
T.
Tung,
S.
Bose,
and
M. M. Crum
Superscalar
Architecture
II
Session Chair: Bob Colwell, Intel
Reducing Wire Delay
Penalty
through
Value
Prediction
.317
J. -M. Parcerisa and
A. González
Compiler Controlled Value Prediction Using Branch Predictor
Based Confidence
.327
E. Larson and T. Austin
Instruction Distribution Heuristics for Quad-Cluster,
Dynamically-Scheduled, Superscalar Processors
.337
Λ.
Baniasadi and A. Moshovos
Performance Improvement with Circuit-Level Speculation
.348
T. Liu and S. -L.
Lu
Author Index
.357
VII |
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| format | Conference Proceeding Book |
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| spelling | Micro 33 2000 Monterey, Calif. Verfasser (DE-588)10024245-5 aut Proceedings 10 - 13 December 2000, Monterey, California, USA 33rd annual IEEE/ACM International Symposium on Microarchitecture, MICRO-33 2000 MICRO-33 MICRO 2000 Proceedings of the 33rd annual IEEE ACM International Symposium on Microarchitecture Los Alamitos, Calif. [u.a.] IEEE Computer Soc. 2000 XIV, 257 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Micro 33 Einzelaufnahme eines Zeitrschr.-Bandes Mikroarchitektur (DE-588)4139308-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Mikroprogrammierung (DE-588)4039231-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2000 Monterey Calif. gnd-content Mikroarchitektur (DE-588)4139308-9 s DE-604 Mikroprozessor (DE-588)4039232-6 s 1\p DE-604 Computerarchitektur (DE-588)4048717-9 s 2\p DE-604 Mikroprogrammierung (DE-588)4039231-4 s 3\p DE-604 Parallelverarbeitung (DE-588)4075860-6 s 4\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009401441&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings 10 - 13 December 2000, Monterey, California, USA Mikroarchitektur (DE-588)4139308-9 gnd Computerarchitektur (DE-588)4048717-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Mikroprozessor (DE-588)4039232-6 gnd Mikroprogrammierung (DE-588)4039231-4 gnd |
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| title | Proceedings 10 - 13 December 2000, Monterey, California, USA |
| title_alt | MICRO-33 MICRO 2000 Proceedings of the 33rd annual IEEE ACM International Symposium on Microarchitecture |
| title_auth | Proceedings 10 - 13 December 2000, Monterey, California, USA |
| title_exact_search | Proceedings 10 - 13 December 2000, Monterey, California, USA |
| title_full | Proceedings 10 - 13 December 2000, Monterey, California, USA 33rd annual IEEE/ACM International Symposium on Microarchitecture, MICRO-33 2000 |
| title_fullStr | Proceedings 10 - 13 December 2000, Monterey, California, USA 33rd annual IEEE/ACM International Symposium on Microarchitecture, MICRO-33 2000 |
| title_full_unstemmed | Proceedings 10 - 13 December 2000, Monterey, California, USA 33rd annual IEEE/ACM International Symposium on Microarchitecture, MICRO-33 2000 |
| title_short | Proceedings |
| title_sort | proceedings 10 13 december 2000 monterey california usa |
| title_sub | 10 - 13 December 2000, Monterey, California, USA |
| topic | Mikroarchitektur (DE-588)4139308-9 gnd Computerarchitektur (DE-588)4048717-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Mikroprozessor (DE-588)4039232-6 gnd Mikroprogrammierung (DE-588)4039231-4 gnd |
| topic_facet | Mikroarchitektur Computerarchitektur Parallelverarbeitung Mikroprozessor Mikroprogrammierung Konferenzschrift 2000 Monterey Calif. |
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