High performance memory communication architectures for coarse grained reconfigurable computing systems:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Kaiserslautern
Univ.
2001
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 352 S. Ill., graph Darst. : 21 cm |
| ISBN: | 3925178562 |
Internformat
MARC
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| 084 | |a DAT 216d |2 stub | ||
| 100 | 1 | |a Herz, Michael |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a High performance memory communication architectures for coarse grained reconfigurable computing systems |c Michael Herz |
| 246 | 1 | |a High performance memory communication architectures for coarse-grained reconfigurable computing systems | |
| 264 | 1 | |a Kaiserslautern |b Univ. |c 2001 | |
| 300 | |a VIII, 352 S. |b Ill., graph Darst. : 21 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 502 | |a Zugl.: Kaiserslautern, Univ., Diss., 2001 | ||
| 650 | 7 | |a Hochschulschrift |2 gtt | |
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
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| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009328384&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009328384 | |
Datensatz im Suchindex
| _version_ | 1816444079211282432 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
TABLE
OF
CONTENTS
ABSTRACT
.V
TABLE
OF
CONTENTS
.
VII
1.
INTRODUCTION
.
1
2.
COARSE-GRAINED
CONFIGURABLE
ARCHITECTURES
.
5
2.1
THE
DP-FPGA
ARCHITECTURE
.
6
2.2
THE
KRESS
ARRAY
1
.
7
2.3
THE
RAPID
ARCHITECTURE
.
9
2.4
THE
MATRIX
ARCHITECTURE
.
10
2.5
THE
RAW
MACHINE
.
13
2.6
THE
PLEIADES
SYSTEM
.
14
2.7
THE
KRESSARRAY-3
.
15
2.8
MORPHOSYS
RECONFIGURABLE
CELL
ARRAY
.
17
2.9
THE
CHESS
ARRAY
.
19
2.10
THE
DREAM
ARRAY
.
21
2.11
CONCLUSIONS
.
22
3.
MEMORY
TECHNOLOGIES
.
25
3.1
CURRENT
MEMORY
DEVICES
SUITABLE
TO
FORM
LARGE
DATA
MEMORIES
.
25
3.1.1
CONCLUSIONS
.
27
3.2
THE
DATA
MEMORY
ORGANIZATION
OF
RECONFIGURABLE
SYSTEMS
.
28
3.2.1
RECONFIGURABLE
SYSTEM
WITH
EXTERNAL
MEMORY
.
29
3.2.2
RECONFIGURABLE
ARCHITECTURE
WITH
VIRTUAL
INTERNAL
MEMORY
.
31
3.2.3
RECONFIGURABLE
ARCHITECTURE
WITH
EMBEDDED
MEMORY
.
31
3.2.4
RECONFIGURABLE
ARCHITECTURE
SURROUNDED
BY
MEMORY
.
34
3.2.5
CONCLUSIONS
.
35
4.
EARLIER
ADDRESS
GENERATORS
.
37
4.1
THE
STRUCTURED
MEMORY
ACCESS
MACHINE
.
38
4.2
THE
ADDRESS
GENERATOR
OF
THE
MAP-ORIENTED
MACHINE
1
.
42
4.3
A
SYNTHESIS
METHOD
FOR
ADDRESS
GENERATORS
.
43
4.4
THE
ADDRESS
GENERATOR
OF
THE
MAP-ORIENTED
MACHINE
2
.
44
4.5
THE
VIDEO
SIGNAL
PROCESSOR
.
47
4.6
THE
ADDRESS
GENERATOR
OF
THE
MAP-ORIENTED
MACHINE
3
.
51
4.7
THE
TEXAS
INSTRUMENTS
TMS320C54X
DSP
.
57
4.8
THE
ADOPT
PROJECT
.
62
4.9
THE
INTERSIL
HSP45240
ADDRESS
SEQUENCER
.
66
4.10
CONCLUSIONS
.
70
TABLE
OF
CONTENTS
5.
RECONFIGURABLE
SYSTEMS
USING
DATA
SEQUENCING
_
.
-------------
73
5.1
THE
PRISM-II
SYSTEM
.
75
5.2
RILEY-2
.
76
5.3
AN
EPLD
BASED
TRANSIENT
RECORDER
FOR
VIDEO
SIGNALS
.
77
5.4
THE
RAPID
DATA
SEQUENCING
METHOD
.
79
5.5
THE
PAR-1
.
79
5.6
THE
REACT
SYSTEM
.
81
5.7
THE
CHAMP
ARCHITECTURE
.
82
5.8
THE
MAP-ORIENTED
MACHINE
1
.
83
5.9
THE
MAP-ORIENTED
MACHINE
2
.
83
5.10
THE
MAP-ORIENTED
MACHINE
3
.
84
5.11
CONCLUSIONS
.
87
6.
A
NOVEL
DATA
SEQUENCING
CONCEPT
.
89
6.1
THE
BASIC
DATA
SEQUENCING
PRINCIPLES
.
90
6.1.1
THE
BASIC
XPUTER
ARCHITECTURE
.
90
6.1.2
A
TWO-LEVEL
ADDRESS
GENERATION
METHOD
.
92
6.1.3
THE
PRINCIPLE
DATA
SEQUENCER
ARCHITECTURE
.
94
6.2
ADDRESS
GENERATION
WITH
THE
SLIDER
METHOD
.
96
6.2.1
THE
VIDEO
SCAN
.
98
6.2.2
THE
COMPOUND
SCAN
.
104
6.2.3
THE
NESTED
SCAN
.
105
6.2.4
THE
MESHED
SCAN
.
106
6.2.5
THE
COMPLEX
SCAN
.
107
6.2.6
SUMMARY
OF
THE
CLASSIFICATION
.
107
6.3
THE
HARDWARE
IMPLEMENTATION
OF
THE
SLIDER
METHOD
.
109
6.3.1
THE
STEPPER
.
109
6.3.2
THE
ONE-DIMENSIONAL
GENERIC
ADDRESS
GENERATOR
.
111
6.3.3
THE
TWO-DIMENSIONAL
VIDEO
SCAN
GENERATOR
.
113
6.4
A
STACK
MECHANISM
FOR
THE
GENERATION
OF
COMPLEX
ADDRESS
SEQUENCES
114
6.5
THE
DATA
SEQUENCER
MAPPED
TO
THE
KRESSARRAY
.
121
6.5.1
MEMORY
COMMUNICATION
MODELS
FOR
THE
KRESSARRAY
.
123
6.5.2
THE
KRESSARRAY
IMPLEMENTATION
OF
THE
DATA
SEQUENCER
.
125
6.5.3
THE
GENERATION
OF
APPLICATION
SPECIFIC
DATA
SEQUENCERS
.
133
6.6
CHAPTER
SUMMARY
.
142
7.
DATA
SEQUENCER
USE
FOR
HIGHER
MEMORY
BANDWIDTH
.
145
7.1
THE
MEMORY
ARCHITECTURE
.
147
7.1.1
ROW
MAJOR
MAPPING
.
148
7.1.2
PARALLEL
MEMORY
BANKS
.
148
7.1.2.1
ROW
MAJOR
MAPPING
WITH
PARALLEL
MEMORY
BANKS
.
149
7.1.2.2
THE
DYNAMIC
ASSIGNMENT
OF
RELATIVE
SCAN
WINDOW
POSITIONS
TO
PARALLEL
MEMORY
BANKS
.
150
7.1.2.3
A
MAPPING
SCHEME
TO
SOLVE
DATA
LOCALITY
COHERENCE
PROBLEMS
.
151
IV
TABLE
OF
CONTENTS
7.1.3
CONSEQUENCES
OF
THE
PRESENTED
MEMORY
ORGANIZATION
.
152
7.1.4
THE
HARDWARE
LEVEL
SUPPORT
FOR
MEMORY
ACCESS
OPTIMIZATION
.153
7.1.4.1
CONCURRENT
ACCESS
TO
PARALLEL
MEMORY
BANKS
.
153
7.1.4.2
THE
SCAN
WINDOW
OVERLAP
OPTIMIZATION
.
155
7.1.4.3
THE
BURST
ACCESS
OPTIMIZATION
.
158
7.1.4.4
SUMMARY
OF
HARDW
ARE
LEVEL
OPTIMIZATIONS
.
160
7.2
LOOP
TRANSFORMATIONS
.
162
7.2.1
INNER
SCAN
LINE
LOOP
UNROLLING
.
162
7.2.2
SCAN
LINE
UNROLLING
.
163
7.3
THE
MODIFICATION
OF
STORAGE
SCHEMES
.
165
7.3.1
THE
LOW
LEVEL
STORAGE
SCHEME
MODIFICATION
.
166
7.3.2
THE
HIGH
LEVEL
STORAGE
SCHEME
MODIFICATION
.
168
7.4
SCHEDULING
OF
MEMORY
ACCESSES
.
174
7.4.1
THE
OPTIMUM
DATA
ACCESS
SCHEDULING
.
175
7.4.2
SCHEDULING
TRADE-OFF
.
177
7.5
THE
OPTIMIZATION
METHOD
.
179
7.6
CHAPTER
SUMMARY
.
181
8.
AN
APPLICATION
EXAMPLE
.
183
8.1
THE
LINEAR
FILTER
APPLICATION
.
184
8.1.1
THE
DESIGN
SPECIFICATION
USING
THE
XMDS
.
186
8.1.2
MOPL
DESCRIPTION
OF
THE
MERGED
BUFFER
LINEAR
FILTER
APPLICATION
188
8.1.3
REQUIRED
MEMORY
CYCLES
OF
THE
MERGED
BUFFER
LINEAR
FILTER
DESIGN
.
189
8.2
THE
HARDWARE
LEVEL
MEMORY
ACCESS
OPTIMIZATION
OF
THE
MERGED
BUFFER
LINEAR
FILTER
APPLICATION
.
189
8.3
THE
SOFTWARE
LEVEL
MEMORY
ACCESS
OPTIMIZATION
OF
THE
MERGED
BUFFER
LINEAR
FILTER
APPLICATION
.
192
8.4
MEMORY
ACCESS
OPTIMIZATION
RESULTS
FOR
THE
PARALLELIZED
MERGED
BUFFER
LINEAR
FILTER
APPLICATION
.
201
8.5
DATA
SEQUENCER
PERFORMANCE
EVALUATION
OF
THE
PARALLELIZED
MERGED
BUFFER
LINEAR
FILTER
APPLICATION
FOR
THE
CPLD-BASED
DATA
SEQUENCER
SOLUTION
.202
8.6
A
PARALLELIZED
LINEAR
FILTER
IMPLEMENTATION
USING
THE
KRESSARRAY-3
.
207
8.6.1
EXAMPLE
IMPLEMENTATION
WITH
DATAPATH
UNITS
OF
CONVENTIONAL
FUNCTIONALITY
.
209
8.6.2
EXAMPLE
IMPLEMENTATION
WITH
HIGHLY
INTEGRATED
MULTI-FUNCTION
DATAPATH
UNITS
.215
8.6.3
THE
LINEAR
FILTER
EXAMPLE
MAPPING
RESULTS
.
217
8.7
CHAPTER
SUMMARY
.217
9.
CONCLUSIONS
.
219
V
TABLE
OF
CONTENTS
APPENDIX
A.
A
DEVELOPMENT
FRAMEWORK
FOR
DATA
SEQUENCERS
.
225
A.
1
THE
INTERNET-BASED
IMPLEMENTATION
.
225
A.2
THE
XPUTER
MULTIMEDIA
DEVELOPMENT
SYSTEM
TOOLS
.
229
A.3
CHAPTER
SUMMARY
.238
B.
THE
MOPL-3
GRAMMAR
.
241
B
.
1
PROGRAM
DEFINITION
.
241
B.2
BOUNDARY
DECLARATIONS
.
241
B.3
SCAN
WINDOW
DECLARATIONS
.
242
B.4
RALU
SET-UP
DECLARATIONS
.
242
B.5
SCAN
PATTERN
DECLARATIONS
.
244
B.6
SCAN
STATEMENT
DECLARATIONS
.
245
B.7
SCAN
ACTION
DECLARATIONS
.
246
B.8
EXPRESSION
DECLARATIONS
.248
B.9
LEXICAL
DECLARATIONS
.
249
B.
10
COMMON
PRODUCTION
RULES
.
250
C.
MULTIBANK
DRAM
TECHNOLOGY
.
253
C.
1
THE
INTERNAL
STRUCTURE
AND
INTERFACES
.253
C.2
THE
MDRAM
COMMANDS
AND
FUNCTIONALITY
.
255
C.3
THE
MEMORY
REFRESH
.
259
D.
THE
MAP-ORIENTED
MACHINE
WITH
PARALLEL
DATA
ACCESS
.
261
D.
1
THE
MOM-PDA
OVERALL
ARCHITECTURE
.
262
D.2
THE
MOM-PDA
DATA
SEQUENCER
.263
D.2.1THE
MOM-PDA
HANDLE
POSITION
GENERATION
.
264
D.2.2THE
MOM-PDA
SCAN
WINDOW
GENERATION
.
269
D.2.3THE
MOM-PDA
MEMORY
MAPPING
.273
D.2.4
INTERFACING
MULTIBANK
DRAM
.
275
D.2.5
MULTITASKING
.
281
D.3
THE
HARDWARE
COMPONENTS
OF
THE
MOM-PDA
.
282
D.3.
1
THE
PCI
INTERFACE
BOARD
.
282
D.3.2THE
MOM-PDA
BOARD
.
283
D.3.2.
1
THE DATA SEQUENCER
.
284
D.3.2.2THE
BURST
CONTROL
UNIT
.
286
D.3.2.3
THE
RECONFIGURABLE
ALU
PORT
.287
D.3.
3
THE
KRESSARRAY
EMULATOR
.293
VI
TABLE
OF
CONTENTS
ACKNOWLEDGMENTS
.
295
CURRICULUM
VITAE
.
297
LIST
OF
FIGURES
.
299
LIST
OF
TABLES
.
311
LIST
OF
DEFINITIONS
.
313
LIST
OF
SYMBOLS
AND
ACRONYMS
.
315
REFERENCES
.
325
INDEX
.
347
VII |
| any_adam_object | 1 |
| author | Herz, Michael |
| author_facet | Herz, Michael |
| author_role | aut |
| author_sort | Herz, Michael |
| author_variant | m h mh |
| building | Verbundindex |
| bvnumber | BV013652718 |
| classification_tum | DAT 406d DAT 416d DAT 216d |
| ctrlnum | (OCoLC)48726312 (DE-599)BVBBV013652718 |
| discipline | Informatik |
| format | Thesis Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV013652718 |
| illustrated | Illustrated |
| indexdate | 2024-11-22T17:21:02Z |
| institution | BVB |
| isbn | 3925178562 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009328384 |
| oclc_num | 48726312 |
| open_access_boolean | |
| owner | DE-12 DE-91 DE-BY-TUM DE-355 DE-BY-UBR DE-739 DE-824 DE-29T DE-634 |
| owner_facet | DE-12 DE-91 DE-BY-TUM DE-355 DE-BY-UBR DE-739 DE-824 DE-29T DE-634 |
| physical | VIII, 352 S. Ill., graph Darst. : 21 cm |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Univ. |
| record_format | marc |
| spelling | Herz, Michael Verfasser aut High performance memory communication architectures for coarse grained reconfigurable computing systems Michael Herz High performance memory communication architectures for coarse-grained reconfigurable computing systems Kaiserslautern Univ. 2001 VIII, 352 S. Ill., graph Darst. : 21 cm txt rdacontent n rdamedia nc rdacarrier Zugl.: Kaiserslautern, Univ., Diss., 2001 Hochschulschrift gtt Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Speicherverwaltung (DE-588)4182146-4 gnd rswk-swf Speicherzugriff (DE-588)4182148-8 gnd rswk-swf Parallelrechner (DE-588)4173280-7 gnd rswk-swf Rekonfiguration (DE-588)4306238-6 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Parallelrechner (DE-588)4173280-7 s Rekonfiguration (DE-588)4306238-6 s Speicherzugriff (DE-588)4182148-8 s DE-604 Computerarchitektur (DE-588)4048717-9 s 1\p DE-604 Speicherverwaltung (DE-588)4182146-4 s 2\p DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009328384&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Herz, Michael High performance memory communication architectures for coarse grained reconfigurable computing systems Hochschulschrift gtt Computerarchitektur (DE-588)4048717-9 gnd Speicherverwaltung (DE-588)4182146-4 gnd Speicherzugriff (DE-588)4182148-8 gnd Parallelrechner (DE-588)4173280-7 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4182146-4 (DE-588)4182148-8 (DE-588)4173280-7 (DE-588)4306238-6 (DE-588)4113937-9 |
| title | High performance memory communication architectures for coarse grained reconfigurable computing systems |
| title_alt | High performance memory communication architectures for coarse-grained reconfigurable computing systems |
| title_auth | High performance memory communication architectures for coarse grained reconfigurable computing systems |
| title_exact_search | High performance memory communication architectures for coarse grained reconfigurable computing systems |
| title_full | High performance memory communication architectures for coarse grained reconfigurable computing systems Michael Herz |
| title_fullStr | High performance memory communication architectures for coarse grained reconfigurable computing systems Michael Herz |
| title_full_unstemmed | High performance memory communication architectures for coarse grained reconfigurable computing systems Michael Herz |
| title_short | High performance memory communication architectures for coarse grained reconfigurable computing systems |
| title_sort | high performance memory communication architectures for coarse grained reconfigurable computing systems |
| topic | Hochschulschrift gtt Computerarchitektur (DE-588)4048717-9 gnd Speicherverwaltung (DE-588)4182146-4 gnd Speicherzugriff (DE-588)4182148-8 gnd Parallelrechner (DE-588)4173280-7 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| topic_facet | Hochschulschrift Computerarchitektur Speicherverwaltung Speicherzugriff Parallelrechner Rekonfiguration |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009328384&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT herzmichael highperformancememorycommunicationarchitecturesforcoarsegrainedreconfigurablecomputingsystems |