Writing testbenches: functional verification of HDL models
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
2001
|
| Ausgabe: | 4. print. |
| Schlagworte: | |
| Beschreibung: | XXII, 354 S. graph. Darst. |
| ISBN: | 0792377664 |
Internformat
MARC
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| 245 | 1 | 0 | |a Writing testbenches |b functional verification of HDL models |c Janick Bergeron |
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| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 2001 | |
| 300 | |a XXII, 354 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Hardwareverifikation |0 (DE-588)4214982-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-009241545 | |
Datensatz im Suchindex
| _version_ | 1806051373264928768 |
|---|---|
| adam_text | |
| any_adam_object | |
| author | Bergeron, Janick |
| author_facet | Bergeron, Janick |
| author_role | aut |
| author_sort | Bergeron, Janick |
| author_variant | j b jb |
| building | Verbundindex |
| bvnumber | BV013536887 |
| classification_rvk | ZN 4030 |
| ctrlnum | (OCoLC)248893481 (DE-599)BVBBV013536887 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 4. print. |
| format | Book |
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| id | DE-604.BV013536887 |
| illustrated | Illustrated |
| indexdate | 2024-07-31T00:13:28Z |
| institution | BVB |
| isbn | 0792377664 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009241545 |
| oclc_num | 248893481 |
| open_access_boolean | |
| owner | DE-92 |
| owner_facet | DE-92 |
| physical | XXII, 354 S. graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Kluwer |
| record_format | marc |
| spelling | Bergeron, Janick Verfasser aut Writing testbenches functional verification of HDL models Janick Bergeron 4. print. Boston [u.a.] Kluwer 2001 XXII, 354 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VERILOG (DE-588)4268385-3 s Hardwareverifikation (DE-588)4214982-4 s DE-604 VHDL (DE-588)4254792-1 s Entwurfsautomation (DE-588)4312536-0 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Bergeron, Janick Writing testbenches functional verification of HDL models Hardwareverifikation (DE-588)4214982-4 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4214982-4 (DE-588)4268385-3 (DE-588)4254792-1 (DE-588)4312536-0 |
| title | Writing testbenches functional verification of HDL models |
| title_auth | Writing testbenches functional verification of HDL models |
| title_exact_search | Writing testbenches functional verification of HDL models |
| title_full | Writing testbenches functional verification of HDL models Janick Bergeron |
| title_fullStr | Writing testbenches functional verification of HDL models Janick Bergeron |
| title_full_unstemmed | Writing testbenches functional verification of HDL models Janick Bergeron |
| title_short | Writing testbenches |
| title_sort | writing testbenches functional verification of hdl models |
| title_sub | functional verification of HDL models |
| topic | Hardwareverifikation (DE-588)4214982-4 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Hardwareverifikation VERILOG VHDL Entwurfsautomation |
| work_keys_str_mv | AT bergeronjanick writingtestbenchesfunctionalverificationofhdlmodels |