Abstract: "There exist many methods for extracting automatically parallelism (sometimes even a provably maximal amount of parallelism) out of a sequential imperative loop program. However, for performance reasons, the granularity of parallelism must be coarse enough in order to get a useful rat...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Griebl, Martin (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Passau 2000
Schriftenreihe:	Universität <Passau> / Fakultät für Mathematik und Informatik: MIP 2000,09
Schlagworte:	Compiling (Electronic computers) Loop tiling (Computer science)
Zusammenfassung:	Abstract: "There exist many methods for extracting automatically parallelism (sometimes even a provably maximal amount of parallelism) out of a sequential imperative loop program. However, for performance reasons, the granularity of parallelism must be coarse enough in order to get a useful ratio between the number of computations and the number of communications. Usually, tiling techniques are applied for obtaining coarser parallelism. Unfortunately, those tiling techniques designed for limiting parallelism can only deal with perfectly nested loops so far (even if there is some recent work which deals with tiling imperfect loop nests for cache optimization; cf. Sectionsec:relwork). Thus, the goal of this paper is to provide a technique which allows imperfectly nested programs as input and produces a well-performing tiled parallel program as output. In contrast to other approaches, we apply tiling techniques not to a (sequential) source program but to its derived parallel, i.e., space-time mapped target program. Therefore, we need no sophisticated tiling techniques for imperfect loop nests, we do not limit the power of the parallelization phase, i.e., the space-timing mapping phase, and we can directly choose the granularity dependent on the number of physically available processors."
Beschreibung:	15, 3 S. Ill.