Writing testbenches: functional verification of HDL models
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
2000
|
| Ausgabe: | 3. print. |
| Schlagworte: | |
| Beschreibung: | XXII, 354 S. graph. Darst. |
| ISBN: | 0792377664 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV013353201 | ||
| 003 | DE-604 | ||
| 005 | 20010918 | ||
| 007 | t | ||
| 008 | 000921s2000 d||| |||| 00||| eng d | ||
| 020 | |a 0792377664 |9 0-7923-7766-4 | ||
| 035 | |a (OCoLC)43031215 | ||
| 035 | |a (DE-599)BVBBV013353201 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 050 | 0 | |a TK7885.7 | |
| 082 | 0 | |a 621.3815 |2 21 | |
| 084 | |a ZN 4030 |0 (DE-625)157339: |2 rvk | ||
| 084 | |a DAT 280f |2 stub | ||
| 100 | 1 | |a Bergeron, Janick |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Writing testbenches |b functional verification of HDL models |c Janick Bergeron |
| 250 | |a 3. print. | ||
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 2000 | |
| 300 | |a XXII, 354 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Computer hardware description languages | |
| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwareverifikation |0 (DE-588)4214982-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 1 | 1 | |a Hardwareverifikation |0 (DE-588)4214982-4 |D s |
| 689 | 1 | |8 1\p |5 DE-604 | |
| 689 | 2 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 2 | 1 | |a Hardwareverifikation |0 (DE-588)4214982-4 |D s |
| 689 | 2 | |8 2\p |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-009107311 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804128129515520000 |
|---|---|
| any_adam_object | |
| author | Bergeron, Janick |
| author_facet | Bergeron, Janick |
| author_role | aut |
| author_sort | Bergeron, Janick |
| author_variant | j b jb |
| building | Verbundindex |
| bvnumber | BV013353201 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4030 |
| classification_tum | DAT 280f |
| ctrlnum | (OCoLC)43031215 (DE-599)BVBBV013353201 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 3. print. |
| format | Book |
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| id | DE-604.BV013353201 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:44:20Z |
| institution | BVB |
| isbn | 0792377664 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009107311 |
| oclc_num | 43031215 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | XXII, 354 S. graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
| publishDateSort | 2000 |
| publisher | Kluwer |
| record_format | marc |
| spelling | Bergeron, Janick Verfasser aut Writing testbenches functional verification of HDL models Janick Bergeron 3. print. Boston [u.a.] Kluwer 2000 XXII, 354 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computer hardware description languages Integrated circuits Verification VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 s DE-604 VHDL (DE-588)4254792-1 s Hardwareverifikation (DE-588)4214982-4 s 1\p DE-604 VERILOG (DE-588)4268385-3 s 2\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Bergeron, Janick Writing testbenches functional verification of HDL models Computer hardware description languages Integrated circuits Verification VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd Hardwareverifikation (DE-588)4214982-4 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4268385-3 (DE-588)4254792-1 (DE-588)4214982-4 (DE-588)4312536-0 |
| title | Writing testbenches functional verification of HDL models |
| title_auth | Writing testbenches functional verification of HDL models |
| title_exact_search | Writing testbenches functional verification of HDL models |
| title_full | Writing testbenches functional verification of HDL models Janick Bergeron |
| title_fullStr | Writing testbenches functional verification of HDL models Janick Bergeron |
| title_full_unstemmed | Writing testbenches functional verification of HDL models Janick Bergeron |
| title_short | Writing testbenches |
| title_sort | writing testbenches functional verification of hdl models |
| title_sub | functional verification of HDL models |
| topic | Computer hardware description languages Integrated circuits Verification VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd Hardwareverifikation (DE-588)4214982-4 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Computer hardware description languages Integrated circuits Verification VERILOG VHDL Hardwareverifikation Entwurfsautomation |
| work_keys_str_mv | AT bergeronjanick writingtestbenchesfunctionalverificationofhdlmodels |