Proceedings: ISPD-2000 ; San Diego, CA, April 9 - 12, 2000
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Assoc. for Computing Machinery
2000
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 215 S. graph. Darst. |
| ISBN: | 1581131917 |
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Datensatz im Suchindex
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|---|---|
| adam_text | Table
of
Contents
Committees
................................................................................................................................................ix
Welcome and Keynote
...........................................................................................................................1
Chair: D. Hill (Synopsys)
Keynote Speaker:
Aart de Geus
(Synopsys)
Session
1:
Technology Trends
............................................................................................................2
Chair:
S. S.
Sapatnekar (Univ. of Minnesota)
Circuit Design Challenges Beyond
0.18
Micron
S. Borkar (Intel)
•
How Thin is the ICE? How Variability and Yield Drive Physical Design
S. Nassif(lBM)
Interconnect Design and Analysis Issues in High Performance ICs
A.Devgan (IBM)
Session
2:
Developments in Routing
................................................................................................3
Chair: P. Groeneveld (Magma)
•
Requirements for Models of Achievable Routing
....................................................................................4
A. B. Kahng, S.
Mant
i k. D.
Stroobandt (UCLA)
DUNE: A Multi-Layer Gridless Routing System with Wire Planning
..................................................12
J. Cong, J. Fang, K.-Y. Khoo (UCLA)
Provably
Good Global Routing by a New Approximation Algorithm for Multicommodity Flow
........19
C.
Albrecht (Univ.
of Bonn)
•
Exact
Switchbox
Routing with Search Space Reduction
.......................................................................26
F. Schmiedle, D.
Unruh,
В.
Becker (Albert-Ludwigs Univ.)
•
Zero-Skew Clock Tree Construction by Simultaneous Routing, Wire Sizing and Buffer Insertion
......33
1-М.
Liu (Univ. of Texas-Austin), T.-L.
Chou
(Intel), A. Aziz and
D. F.
Wong (Univ. of Texas-Austin)
Panel
1:
The Bottom-10 Problems in EDA
..................................................................................39
Organizer and Chair:
N.
Sherwani (Intel)
Session
3:
Issues in Interconnect
.....................................................................................................40
Chair: R. Often (Delft Univ.)
Pseudo
Pin Assignment with Crosstalk Noise Control
..........................................................................41
C.-C. Chang. J. Cong (UCLA)
•
Aggressor Alignment for Worst-Case Coupling Noise
..........................................................................48
L.H. Chen, M. Marek-Sadowska (UCSB)
•
Simultaneous Shield Insertion and Net Ordering for
Capacitive
and Inductive
Coupling Minimization
...........................................................................................................................55
L. He, K. M. Lepak (Univ. of Wisconsin)
•
Wire Packing: A Strong Formulation of Crosstalk-Aware Chip-Level Track/Layer
Assignment with an Efficient Integer Programming Solution
...............................................................61
R. Kay (Intel), R. A.
Rutenbar
(С
MU)
A Two Moment RC Delay Metric for Performance Optimization
.........................................................69
С
J. Alpert, A. Devgan,
С
Kashyap (IBM)
Session
4:
Challenges for EDA
-
Analog and Incremental
75
Chair: M. Pedram
(USC)
Layout Tools for Analog ICs and Mixed-Signal SoCs: A Survey
.........................................................76
R.
Rutenbar
(CMU), J. M. Cohn (IBM)
Incremental Physical Design
..................................................................................................................
84
J. Cong, (UCLA), M. Sarrafzadeh (Northwestern U)
Session
5:
Expanding the Realm of Physical Design
93
Chair: R.
Rutenbar (CMU)
Itanium™ Processor Clock Design
........................................................................................................94
U. Desai, S. Tarn, R. Kim, J. Zhang, S.
Rusu
(Intel)
•
Methodology for Repeater Insertion Management in the
RTL,
Layout, Floorplan
and Fullchip Timing Databases of the Itanium™ Microprocessor
.........................................................99
R. Mclnerney,, K. Leeper, T. Hill, H. Chan, B.
Basaran,
L.
McQuiddy (Intel)
•
Buffer Minimization in Pass Transistor Logic
.....................................................................................105
H. Zhou (Synopsys), A. Aziz
(UT-
Austin)
A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis
..........111
M. Hashimoto, H. Onodera (Kyoto U.)
Simulating Frequency-Dependent Current Distribution for Inductance Modeling
ofOn-Chip Copper Interconnects
.........................................................................................................117
L.-F. Chang, K.-J. Chang, R. Mathews (Frequency Technology)
Session
6:
Poster Papers
....................................................................................................................121
Chair: J. Lillis (U. Illinois-Chicago)
Datapath Routing Based on a Decongestion Metric
.............................................................................122
S. Raman, S. S. Sapatnekar (U. Minnesota),
C.
J. Alpert (IBM)
Optimal Reliable Crosstalk Driven Interconnect Optimization
............................................................128
/.
Н
-R.
Jiang, S.-R. Pan, Y.-W. Chang, J.-Y.
Jou
(National Chiao-Tung U.)
A Hybrid Dynamic
/
Quadratic Programming Algorithm for Interconnect Tree Optimization
..........134
Y.-Y. Mo,
С. С.
N.
Chu
(Iowa
State
U.)
Critical Area Computation for Missing Material Defects in VLSI Circuits
.........................................140
E. Papadopoulou (IBM)
Multi-Center Congestion Estimation and Minimization During Placement
.........................................147
M. Wang, X. Yang, K. Eguro, M. Sarrafzadeh (Northwestern U.)
A Snap-On Placement Tool
............................................
j53
A . Yang, M. Wang, K. Eguro, M. Sarrafzadeh (Northwestern U.)
•
A Practical Clock Tree Synthesis for Semi-Synchronous Circuit
................ 159
Л/.
Toyonaga, K. Kurokawa, T. Yasui (Matsushita), A. Takahashi (Tokyo Institute)
........................
vi
Panel
2:
EDA
and the Internet
.......................................................................................................165
Organizer and Chair: D. Hill (Synopsys)
Panelists: Mark Gilbreath (Toolwire), Wayne
Heideman
(Synopsys),
George
J
anac (InTime), and Adriaan Ligtenberg (Cadence)
Session
7:
Floorplanning and Partitioning
................................................................................167
Chair:
C. J. Alpert
(IBM)
•
An Enhanced Perturbing Algorithm for Floorplan Design Using the
О
-tree
Representation
..............168
Y. Pang, C.-K. Cheng (UCSD), T. Yoshimura (NEC)
Floorplan Area Minimization using Lagrangian Relaxation
...............................................................174
F. Y. Young (Chinese U. of Hong Kong),
С. С.
N.
Chu
(Iowa
State
U.),
W.
S.
Luk,
Y. C
Wong (Synopsys)
•
Planning Buffer Locations by Network Flows
.....................................................................................180
X. Tang, D. F. Wong
(UT-
Austin)
•
Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning
........................186
P.
Särkar,
V. Sundararaman, C.-K. Koh (Purdue U.)
•
Multilevel Cooperative Search: Application to the Circuit
/
Hypergraph Partitioning Problem
..........192
M. Ouyang (U. Nebraska-Lincoln), M. Toulouse (U. Manitoba), K. Thulasiraman (U. Oklahomw),
F. Glover (U. Colorado), J. Deogun (U. Nebraska-Lincoln)
Session
8:
Complexity and Overlapping Design Space
........................................................199
Chair: J. Jess (Eindhoven)
•
Coping with Physical Design Problem Sizes in the Post-Moore s Law Era
T.
Gao,
P. Parakh (Monterey)
•
Physopt
S. Krishnamoorty, S. Thakur (Synopsys)
Session
9:
Floorplanning: Use and Abuse
..................................................................................200
Organizer and Chair: P. Groeneveld (Magma)
What is a Floorplan?
............................................................................................................................201
R. Otten (TU-Delft)
•
Classical Floorplanning Harmful?
........................................................................................................207
A. B. Kahng (UCLA)
Panel Discussion: The Right Floorplanning Formulations for Future Chip
Implementation Methodologies
.................................................................214
Moderator: P. Groeneveld (Magma)
Panelists: Jacob Greidinger
(Aristo
Design), George Janac (InTime Software), Wilm Donath (IBM)
Author Index
.........................................................................................................................................215
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| spelling | International Symposium on Physical Design 4 2000 San Diego, Calif. Verfasser (DE-588)10008517-9 aut Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 International Symposium on Physical Design, 2000 New York, NY Assoc. for Computing Machinery 2000 VIII, 215 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computer-aided design Congresses VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2000 San Diego Calif. gnd-content VLSI (DE-588)4117388-0 s CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009058035&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 Computer-aided design Congresses VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 |
| title_auth | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 |
| title_exact_search | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 |
| title_full | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 International Symposium on Physical Design, 2000 |
| title_fullStr | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 International Symposium on Physical Design, 2000 |
| title_full_unstemmed | Proceedings ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 International Symposium on Physical Design, 2000 |
| title_short | Proceedings |
| title_sort | proceedings ispd 2000 san diego ca april 9 12 2000 |
| title_sub | ISPD-2000 ; San Diego, CA, April 9 - 12, 2000 |
| topic | Computer-aided design Congresses VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Computer-aided design Congresses VLSI CAD Konferenzschrift 2000 San Diego Calif. |
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