Computer aided verification: 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings
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| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London
Springer
2000
|
| Series: | Lecture notes in computer science
1855 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | X, 582 S. |
| ISBN: | 3540677704 |
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MARC
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| 245 | 1 | 0 | |a Computer aided verification |b 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings |c E. Allen Emerson ; A. Prasad Sistla (ed.) |
| 264 | 1 | |a Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London |b Springer |c 2000 | |
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| 490 | 1 | |a Lecture notes in computer science |v 1855 | |
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| 650 | 4 | |a Logiciels - Vérification - Congrès | |
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| 650 | 7 | |a déduction automatique |2 inriac | |
| 650 | 7 | |a démonstration théorème |2 inriac | |
| 650 | 7 | |a méthode formelle |2 inriac | |
| 650 | 7 | |a méthode vérification |2 inriac | |
| 650 | 7 | |a validation modèle |2 inriac | |
| 650 | 7 | |a vérification automatique |2 inriac | |
| 650 | 4 | |a Computer software |x Verification |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Verification |v Congresses | |
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Record in the Search Index
| _version_ | 1820874891927224320 |
|---|---|
| adam_text |
TABLE
OF
CONTENTS
INVITED
TALKS
AND
TUTORIALS
KEYNOTE
ADDRESS:
ABSTRACTION,
COMPOSITION,
SYMMETRY,
AND
A
LITTLE
DEDUCTION:
THE
REMEDIES
TO
STATE
EXPLOSION
.
1
A.
PNUELI
INVITED
ADDRESS:
APPLYING
FORMAL
METHODS
TO
CRYPTOGRAPHIC
PROTOCOL
ANALYSIS
.
2
C.
MEADOWS
INVITED
TUTORIAL:
BOOLEAN
SATISFIABILITY
ALGORITHMS
AND
APPLICATIONS
IN
ELECTRONIC
DESIGN
AUTOMATION
.
3
J.
MARQUES-SILVA,
K.
SAKALLAH
INVITED
TUTORIAL:
VERIFICATION
OF
INFINITE-STATE
AND
PARAMETERIZED
SYSTEMS
.
4
P.A.
ABDULLA,
B.
JONSSON
REGULAR
PAPERS
AN
ABSTRACTION
ALGORITHM
FOR
THE
VERIFICATION
OF
GENERALIZED
C-SLOW
DESIGNS
5
J.
BAUMGARTNER,
A.
TRIPP,
A.
AZIZ,
V.
SINGHAL,
F.
ANDERSEN
ACHIEVING
SCALABILITY
IN
PARALLEL
REACHABILITY
ANALYSIS
OF
VERY
LARGE
CIRCUITS
20
T.
HEYMAN,
D.
GEIST,
0.
GRUMBERG,
A.
SCHUSTER
AN
AUTOMATA-THEORETIC
APPROACH
TO
REASONING
ABOUT
INFINITE-STATE
SYSTEMS
.
36
0.
KUPFERMAN,
M.
Y.
VARDI
AUTOMATIC
VERIFICATION
OF
PARAMETERIZED
CACHE
COHERENCE
PROTOCOLS
.
53
G.
DELZANNO
BINARY
REACHABILITY
ANALYSIS
OF
DISCRETE
PUSHDOWN
TIMED
AUTOMATA
.
69
Z.
DANG,
O.H.
IBARRA,
T.
BULTAN,
R.A.
KEMMERER,
J.
SU
BOOLEAN
SATISFIABILITY
WITH
TRANSITIVITY
CONSTRAINTS
.
85
R.E.
BRYANT,
M.N.
VELEV
BOUNDED
MODEL
CONSTRUCTION
FOR
MONADIC
SECOND-ORDER
LOGICS
.
99
A.
AYARI,
D.
BASIN
BUILDING
CIRCUITS
FROM
RELATIONS
.
113
J.H.
KUKULA,
T.R.
SHIPLE
VIII
TABLE
OF
CONTENTS
COMBINING
DECISION
DIAGRAMS
AND
SAT
PROCEDURES
FOR
EFFICIENT
SYMBOLIC
MODEL
CHECKING
.
124
P.F.
WILLIAMS,
A.
BIERE,
E.M.
CLARKE,
A.
GUPTA
ON
THE
COMPLETENESS
OF
COMPOSITIONAL
REASONING
.
139
K.S.
NAMJOSHI,
R.J.
TREFLER
COUNTEREXAMPLE-GUIDED
ABSTRACTION
REFINEMENT
.
154
E.
CLARKE,
O.
GRUMBERG,
S.
JHA,
Y.
LU,
H.
VEITH
DECISION
PROCEDURES
FOR
INDUCTIVE
BOOLEAN
FUNCTIONS
BASED
ON
ALTERNATING
AUTOMATA
.
170
A.
AYARI,
D.
BASIN,
F.
KLAEDTKE
DETECTING
ERRORS
BEFORE
REACHING
THEM
.
186
L.
DE
ALFARO,
T.A.
HENZINGER,
F.Y.C.
MANG
A
DISCRETE
STRATEGY
IMPROVEMENT
ALGORITHM
FOR
SOLVING
PARITY
GAMES
.
202
J.
VOGE,
M.
JURDZINSKI
DISTRIBUTING
TIMED
MODEL
CHECKING
-
HOW
THE
SEARCH
ORDER
MATTERS
.
216
G.
BEHRMANN,
T.
HUNE,
F.
VAANDRAGER
EFFICIENT
ALGORITHMS
FOR
MODEL
CHECKING
PUSHDOWN
SYSTEMS
.
232
J.
ESPARZA,
D.
HANSEL,
P.
ROSSMANITH,
S.
SCHWOON
EFFICIENT
BIICHI
AUTOMATA
FROM
LTL
FORMULAE
.
248
F.
SOMENZI,
R.
BLOEM
EFFICIENT
DETECTION
OF
GLOBAL
PROPERTIES
IN
DISTRIBUTED
SYSTEMS
USING
PARTIAL-ORDER
METHODS
.
264
S.D.
STOLLER,
L.
UNNIKRISHNAN,
Y.A.
LIU
EFFICIENT
REACHABILITY
ANALYSIS
OF
HIERARCHICAL
REACTIVE
MACHINES
.
280
R.
ALUR,
R.
GROSU,
M.
MCDOUGALL
FORMAL
VERIFICATION
OF
VLIW
MICROPROCESSORS
WITH
SPECULATIVE
EXECUTION
.
296
M.N.
VELEV
INDUCTION
IN
COMPOSITIONAL
MODEL
CHECKING
.
312
K.L.
MCMILLAN,
S.
QADEER,
J.B.
SAXE
LIVENESS
AND
ACCELERATION
IN
PARAMETERIZED
VERIFICATION
.
328
A.
PNUELI,
E.
SHAHAR
MECHANICAL
VERIFICATION
OF
AN
IDEAL
INCREMENTAL
ABR
CONFORMANCE
ALGORITHM
.
344
M.
RUSINOWITCH,
S.
STRATULAT,
F.
KLAY
TABLE
OF
CONTENTS
IX
MODEL
CHECKING
CONTINUOUS-TIME
MARKOV
CHAINS
BY
TRANSIENT
ANALYSIS
.
358
C.
BAIER,
B.
HAVERKORT,
H.
HERMANNS,
J.-P.
KATOEN
MODEL-CHECKING
FOR
HYBRID
SYSTEMS
BY
QUOTIENTING
AND
CONSTRAINTS
SOLVING
.
373
F.
CASSEZ,
F.
LAROUSSINIE
PRIORITIZED
TRAVERSAL:
EFFICIENT
REACHABILITY
ANALYSIS
FOR
VERIFICATION
AND
FALSIFICATION
.
389
R.
FRAER,
G.
KAMHI,
B.
ZIV,
M.Y.
VARDI,
L.
FIX
REGULAR
MODEL
CHECKING
.
403
A.
BOUAJJANI,
B.
JONSSON,
M.
NILSSON,
T.
TOUILI
SYMBOLIC
TECHNIQUES
FOR
PARAMETRIC
REASONING
ABOUT
COUNTER
AND
CLOCK
SYSTEMS
.
419
A.
ANNICHINI,
E.
A
SARIN,
A.
BOUAJJANI
SYNTACTIC
PROGRAM
TRANSFORMATIONS
FOR
AUTOMATIC
ABSTRACTION
.
435
K.S.
NAMJOSHI,
R.P.
KURSHAN
TEMPORAL-LOGIC
QUERIES
.
450
W.
CHAN
ARE
TIMED
AUTOMATA
UPDATABLE?
.
464
P.
BOUYER,
C.
DUFOURD,
E.
FLEURY,
A.
PETIT
TUNING
SAT
CHECKERS
FOR
BOUNDED
MODEL
CHECKING
.
480
O.
SHTRICHMAN
UNFOLDINGS
OF
UNBOUNDED
PETRI
NETS
.
495
P.A.
ABDULLA,
S.P.
IYER,
A.
NYLEN
VERIFICATION
DIAGRAMS
REVISITED:
DISJUNCTIVE
INVARIANTS
FOR
EASY
VERIFICATION
.
508
J.
RUSHBY
VERIFYING
ADVANCED
MICROARCHITECTURES
THAT
SUPPORT
SPECULATION
AND
EXCEPTIONS
.
521
R.
HOSABETTU,
G.
GOPALAKRISHNAN,
M.
SRIVAS
TOOL
PAPERS
FOCS:
AUTOMATIC
GENERATION
OF
SIMULATION
CHECKERS
FROM
FORMAL
SPECIFICATIONS
.
538
Y.
ABARBANEL,
I.
BEER,
L.
GLUHOVSKY,
S.
KEIDAR,
Y.
WOLFSTHAL
IF:
A
VALIDATION
ENVIRONMENT
FOR
TIMED
ASYNCHRONOUS
SYSTEMS
.
543
M.
BOZGA,
J.-C.
FERNANDEZ,
L.
GHIRVU,
S.
GRAF,
J.-P.
KRIMM,
L.
MOUNIER
X
TABLE
OF
CONTENTS
INTEGRATING
WS1S
WITH
PVS
.
548
S.
OWRE,
H.
RUEFL
P
ET
:
AN
INTERACTIVE
SOFTWARE
TESTING
TOOL
.
552
E.
GUNTER,
R.
KURSHAN,
D.
PELED
A
PROOF-CARRYING
CODE
ARCHITECTURE
FOR
JAVA
.
557
C.
COLBY,
P.
LEE,
G.C.
NECULA
THE
S
TATEMATE
VERIFICATION
ENVIRONMENT
-
MAKING
IT
REAL
.
561
T.
BIENMULLER,
W.
DAMM,
H.
WITTKE
TAPS:
A
FIRST-ORDER
VERIFIER
FOR
CRYPTOGRAPHIC
PROTOCOLS
.
568
E.
COHEN
VINAS-P:
A
TOOL
FOR
TRACE
THEORETIC
VERIFICATION
OF
TIMED
ASYNCHRONOUS
CIRCUITS
.
572
T.
YONEDA
XMC:
A
LOGIC-PROGRAMMING-BASED
VERIFICATION
TOOLSET
.
576
C.R.
RAMAKRISHNAN,
I.
V.
RAMAKRISHNAN,
S.A.
SMOLKA,
Y.
DONG,
X.
DU,
A.
ROYCHOUDHURY,
V.N.
VENKATAKRISHNAN
AUTHOR
INDEX
.
581 |
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| format | Conference Proceeding Book |
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| illustrated | Not Illustrated |
| indexdate | 2025-01-10T15:06:57Z |
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| institution_GND | (DE-588)2184141-X |
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| publishDate | 2000 |
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| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings E. Allen Emerson ; A. Prasad Sistla (ed.) Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London Springer 2000 X, 582 S. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 1855 Circuits intégrés - Essais - Congrès ram Circuits intégrés - Vérification - Congrès Logiciels - Essais - Congrès ram Logiciels - Vérification - Congrès Software gtt Verificatie gtt déduction automatique inriac démonstration théorème inriac méthode formelle inriac méthode vérification inriac validation modèle inriac vérification automatique inriac Computer software Verification Congresses Integrated circuits Verification Congresses Verifikation (DE-588)4135577-5 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2000 Chicago Ill. gnd-content Verifikation (DE-588)4135577-5 s DE-604 Emerson, E. Allen Sonstige oth CAV 12 2000 Chicago, Ill. Sonstige (DE-588)2184141-X oth Lecture notes in computer science 1855 (DE-604)BV000000607 1855 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009007540&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings Lecture notes in computer science Circuits intégrés - Essais - Congrès ram Circuits intégrés - Vérification - Congrès Logiciels - Essais - Congrès ram Logiciels - Vérification - Congrès Software gtt Verificatie gtt déduction automatique inriac démonstration théorème inriac méthode formelle inriac méthode vérification inriac validation modèle inriac vérification automatique inriac Computer software Verification Congresses Integrated circuits Verification Congresses Verifikation (DE-588)4135577-5 gnd |
| subject_GND | (DE-588)4135577-5 (DE-588)1071861417 |
| title | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings |
| title_auth | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings |
| title_exact_search | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings |
| title_full | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings E. Allen Emerson ; A. Prasad Sistla (ed.) |
| title_fullStr | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings E. Allen Emerson ; A. Prasad Sistla (ed.) |
| title_full_unstemmed | Computer aided verification 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings E. Allen Emerson ; A. Prasad Sistla (ed.) |
| title_short | Computer aided verification |
| title_sort | computer aided verification 12th international conference cav 2000 chicago il usa july 15 19 2000 proceedings |
| title_sub | 12th international conference, CAV 2000, Chicago, IL, USA, July 15 - 19, 2000 ; proceedings |
| topic | Circuits intégrés - Essais - Congrès ram Circuits intégrés - Vérification - Congrès Logiciels - Essais - Congrès ram Logiciels - Vérification - Congrès Software gtt Verificatie gtt déduction automatique inriac démonstration théorème inriac méthode formelle inriac méthode vérification inriac validation modèle inriac vérification automatique inriac Computer software Verification Congresses Integrated circuits Verification Congresses Verifikation (DE-588)4135577-5 gnd |
| topic_facet | Circuits intégrés - Essais - Congrès Circuits intégrés - Vérification - Congrès Logiciels - Essais - Congrès Logiciels - Vérification - Congrès Software Verificatie déduction automatique démonstration théorème méthode formelle méthode vérification validation modèle vérification automatique Computer software Verification Congresses Integrated circuits Verification Congresses Verifikation Konferenzschrift 2000 Chicago Ill. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009007540&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
| work_keys_str_mv | AT emersoneallen computeraidedverification12thinternationalconferencecav2000chicagoilusajuly15192000proceedings AT cavchicagoill computeraidedverification12thinternationalconferencecav2000chicagoilusajuly15192000proceedings |