FPGA '00: ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000]
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| Corporate Author: | |
|---|---|
| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
New York, NY
Assoc. for Computing Machinery
2000
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | VII, 223 S. Ill., graph. Darst. |
| ISBN: | 1581131933 |
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MARC
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Table
of Contents
Session
1.
FPGA Architectures
Chair: Sinan Kaptanoglu, Adaptive Silicon
1.1
The Effect of
LUT
and Cluster Size on Deep-Submicron FPGA
Performance and Density.
Elias
Ahmed, Jonathon Rose, University of
Toronto
. 3
1.2
Programmable Memory Blocks Supporting Content-Addressable
Memory. Frank
Heile,
Andrew Leaver, Kerry Veenstra,
Altera
. 13
1.3
A Novel High Throughput
Reconfigurable FPGA
Architecture.
Amit
Singh,
Luca Macchiando,
Arindam Mukherjee,
Małgorzata Marek-Sadowska,
University of California, Santa Barbara
. 22
Session!. Cryptography
Chair: Tom Kean, Algotronix
2.1
Extended Presentation: An FPGA Implementation and Performance
Evaluation of the Serpent Block Cipher. AJ Elbirt,
С
Paar,
Worcester
Polytechnic Institute
. 33
2.2
Factoring Large Numbers with Programmable Hardware. Hea Joung Kim
and William H. Mangione-Smith, University of California, Los Angeles
. 41
Session
3.
Technology Mapping
Chair: Mike Bershteyn, Quickturn
3.1
Technology Mapping for k/m-macrocell Based FPGAs. Jason Cong,
Hui
Huang, Xin Yuan, University of California, Los Angeles
. 51
3.2
Technology Mapping Issues for an FPGA with Lookup Tables and PLA-
like Blocks. Alireza Kaviani, Xilinx; Stephen Brown, University of Toronto.
. 60
3.3
Heterogeneous Technology Mapping for FPGAs with Dual-Port
Embedded Memory Arrays. Steven J.E. Wilton, University of British
Columbia
. 67
3.4
Synthesis for FPGAs with Embedded Memory Blocks. Jason Cong,
Kenneth Yan, University of California, Los Angeles
. 75
Session 4.
Reconfigurable
Computing Systems
Chair:
David Lewis,
University of
Toronto
4.1
A Reconfigurable
Multi-function Computing Cache Architecture. Hue-
Sung Kim,
Aran
К.
Somani, Akhilesh Tyagi, Iowa State University
. 85
4.2
А С
Compiler for a Processor with
a Reconfigurable
Functional Unit.
Alex Ye, Nagaraj Shenoy, Prith
viraj
Banerjee, Northwestern University
. 95
Panel: The John Henry Syndrome:
Humans vs. Machines as FPGA Designers
Moderator: Herman Schmit, Carnegie Mellon University
. 101
Session
5.
Reconfigurable
Computing Applications
Chair: Mike Butts, Synopsys
5.1
A Representation for Dynamic Graphs in
Reconfigurable
Hardware and
Its Application to Fundamental Graph Algorithms.
Lorenz Huelsbergen,
Bell Labs, Lucent Technologies
. 105
5.2
The Application of Genetic Algorithms to the Design of
Reconfigurable
Reasoning VLSI Chips. Moritoshi Yasunaga, University of Tsukuba; Jung
Hwan Kim, University of Louisiana; Ekuo Yoshihara,
Miyazaki
University
. 116
5.3
A Benchmark Suite for Evaluating Configurable Computing Systems
—
Status, Reflections, and Future Directions. S. Kumar, L.
Pires, S.
Ponnuswamy,
С.
Nanavati,
J.
Golusky,
M.
Vojta,
S. Wadi,
D.
Pandalai,
Honeywell
Technology Center; H.
Spaanenburg,
Mercury
Computer Systems,
Inc
. 126
Session
6.
Networks and Communications
Chair:
Ray
Andraka, Andraka Consulting
6.1
Field Programmable Port Extender (FPX) for Distributed Routing and
Queuing. John W.
Lockwood,
Jon S. Turner, David E. Taylor, Washington
University
. 137
6.2
Implementing a RAKE Receiver for Wireless Communications on an
FPGA-based Computer System.
Ali M Shankiti,
Motorola; Miriam Leeser,
Northeastern University
. 145
VI
Session 7.
Issues
in
Programmable
Routing
Chair:
Russ Tessier,
University
of Massachusetts
-
Amherst
7.1
Generating Highly-Routable Sparse Crossbars for PLDs. Guy
G.F.
Lemieux, Paul Leventis, David Lewis,
University of
Toronto. 155
7.2 New Parallelization
and Convergence Results for
NC: A
Negotiation-
Based FPGA Router.
Рак К.
Chan,
Martine D.F. Schlag,
University of
California, Santa Cruz
. 165
7.3
Automatic Generation of FPGA Routing Architectures from High-Level
Descriptions. Vaughn Betz, Jonathon Rose, University of Toronto
. 175
Session
8.
Fault Tolerance, Power Estimation, and Placement
Chair:
Martine Schlag,
University of California
-
Santa Cruz
8.1
Tolerating Operational Faults in Cluster-based FPGAs. Vijay Lakamraju,
Russell Tessier, University of Massachusetts, Amherst
. 187
8.2
Power Estimation Approach for SRAM-based FPGAs.
Karlheinz Weiß,
Carsten Oetker, Igor Katchan, Thorsten Steckstor,
University of
Karlsruhe;
Wolfgang Rosenstiel,
University of
Tübingen. 195
8.3
Timing-Driven Placement for FPGAs. Alexander (Sandy) Marquardt,
Vaughn Betz, Jonathan Rose, Right Track CAD
. 203
Poster Paper Abstracts
. 215
Author Index
. 223 |
| any_adam_object | 1 |
| author_corporate | FPGA Monterey, Calif |
| author_corporate_role | aut |
| author_facet | FPGA Monterey, Calif |
| author_sort | FPGA Monterey, Calif |
| building | Verbundindex |
| bvnumber | BV013180627 |
| classification_rvk | SS 2000 |
| classification_tum | DAT 195f |
| ctrlnum | (OCoLC)634602080 (DE-599)BVBBV013180627 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| id | DE-604.BV013180627 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:20:43Z |
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| isbn | 1581131933 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008980254 |
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| physical | VII, 223 S. Ill., graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
| publishDateSort | 2000 |
| publisher | Assoc. for Computing Machinery |
| record_format | marc |
| spelling | FPGA 8 2000 Monterey, Calif. Verfasser (DE-588)10007300-1 aut FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] FPGA 2000 New York, NY Assoc. for Computing Machinery 2000 VII, 223 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift 2000 Monterey Calif. gnd-content Programmierbare Logikschaltung gnd rswk-swf Programmierbare Logikschaltung f DE-604 Association for Computing Machinery Special Interest Group on Design Automation Sonstige (DE-588)10620-3 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008980254&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| subject_GND | (DE-588)1071861417 |
| title | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| title_alt | FPGA 2000 |
| title_auth | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| title_exact_search | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| title_full | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| title_fullStr | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| title_full_unstemmed | FPGA '00 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| title_short | FPGA '00 |
| title_sort | fpga 00 acm sigda international symposium on field programmable gate arrays monterey california february 9 11 2000 |
| title_sub | ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 9 - 11, 2000] |
| topic_facet | Konferenzschrift 2000 Monterey Calif. Programmierbare Logikschaltung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008980254&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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