Digest of technical papers: November 7 - 11, 1999, San Jose, California
Gespeichert in:
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York
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1999
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIV, 613 S. Ill., graph. Darst. |
| ISBN: | 0780358325 0780358333 0780358341 |
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| 245 | 1 | 0 | |a Digest of technical papers |b November 7 - 11, 1999, San Jose, California |c 1999 IEEE/ACM International Conference on Computer-Aided Design |
| 246 | 1 | 3 | |a ICCAD 99 |
| 246 | 1 | 3 | |a Proceeding of the 1999 International Conference on Computer-Aided Design |
| 246 | 1 | 3 | |a IEEE ACM digest of technical papers |
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Datensatz im Suchindex
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| adam_text |
Table
of
Contents
Foreword
.
ш
Conference Committee
.xiv
Technical Program Committee
.xv
Reviewers
.xvii
Tutorial
1:
Mixed-Signal Design: CAD, Methodology, Case Studies
.xix
Tutorial
2:
Modern Physical Design:
.xx
Algorithm, Technology and Methodology
Tutorial
3:
Low Voltage/Low Power Design Methodologies and CAD
. xxi
Tutorial
4:
Signal Integrity in High Performance Design
.xxii
Panel: CAD Roadmaps
-
Useful, Redundant or Even Obstructive?
.xxiii
Panel: System Level Design: Designers' Wish List vs. Reality
.xxiv
Session 1A: Sequential and Datapath Optimization
Moderators:
Narendra
V. Shenoy, Synopsys, Inc., Mountain View, CA;
Maurizio
Damiani, C2 Design Automation, Santa Clara, CA
1A.1 MARSH:
Min-
Area Retiming with Setup and Hold Constraints
.2
Vijay Sundararajan,
Sachin
S.
Sapatnekar, Keshab K.
Partii
1A.2
OPTIMISTA:
State Minimization of Asynchronous FSMs
.7
for Optimum Output Logic
Robert M.
Fuhrer,
Steven M. Nowick
1A.3 Bit-Level Arithmetic Optimization for Carry-Save Additions
.14
Kei-Yong Khoo, Zhan Yu, Alan
N.
Willson, Jr.
Session IB: Placement I
Moderator:
Carl Sechen,
University of Washington, Seattle, WA
1B.1 Attractor-Repeller Approach for Global Placement
.20
Hussein Etawil, Shawki Areibi, Anthony Vannelli
1B.2 Cell Replication and Redundancy Elimination During Placement for
.25
Cycle Time Optimization
Ingmar
Neumann,
Dominik Stoffel, Hendrik
Hartje, Wolfgang
Kunz
1B3 Concurrent Logic
Restructuring and
Placement
for
Timing
Closure
.31
Jinan Lou, Wei Chen,
Massoud
Pearam
Session 1С:
BDDs in
Formal
Verification
Moderators: Andreas Kuehlmann, IBM Corporation,
Yorktown
Heights, NY;
David
L·
Dill, Stanford
University,
Stanford, CA
ICI
Implicit
Enumeration of Strongly Connected Components
.37
AiguoXie, Peter
A. Beerei
ICI
Least
Fixpoint
Approximations for Reachability Analysis
.41
In
-Но
Moon, James Kukula, Tom Shiple,
Fabio Somenzi
1C.3 Lazy Group Sifting for Efficient Symbolic State Traversal of FSMs
.45
Hiroyuki Higuchi,
Fabio
Somenzi
1C.4 Efficient Manipulation Algorithms for Linearly Transformed BDDs
.50
Wolfgang
Günther, Rolf Drechsler
Session ID: Analog and Mixed-Signal
Moderators: Balsha Robert Stanisic, IBM Corporation, Rochester, MN;
Ramesh Harjani, University of Minnesota, Minneapolis, MN
1D.1 Noise Analysis of Non-Autonomous Radio Frequency Circuits
.55
Amit
Mehrotra, Alberto L. Sangiovanni-Vincentelli
1D.2 New Methods for Speeding up Computation of Newton Updates
.61
in Harmonic Balance
M. Gourary, S. Ulyanov, M. Zharov, S. Rusakov, K. Gullapalli, B. Mulvaney
1D.3 Design and Optimization of LC Oscillators
.65
Maria del Mar Hershenson,
Ali
Hajimiri, Sunderarajan S. Mohan, Stephen P. Boyd,
Thomas H. Lee
1D.4 Modeling and Simulation of the Interference due to Digital Switching
.70
in Mixed-Signal ICs
Alper
Demir, Peter
Feldmann
Session 2A: Power Optimization
Moderators:
Renu
Mehra, Synopsys, Inc., Mountain View, CA;
Luca
Benini,
University of Bologna, Bologna, Italy
2A.1
Provably
Good Algorithm for Low Power Consumption with
.76
Dual Supply Voltages
Chunhong Chen, Majid Sarrafzadeh
2A.2 A Novel Design Methodology for High Performance and Low Power
.80
Digital Filters
Khurram Muhammad, Kaushik Roy
2A.3 A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits
.84
Shanq-Jang Ruan, Rung
-Л
Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang
Session 2B: Placement II
Moderators: Majid Sarrafzadeh, Northwestern University, Evanston,
IL;
Gary Yeap, Monterey Design Systems, Inc., Sunnyvale, CA
2B.1
AKORD:
Transistor Level and Mixed Transistor
/
Gate Level Placement
.91
Tool for Digital Data Paths
Tatjana
Serdar,
Carl Sechen
2B.2
Analytical Approach to Custom Datapath Design
.98
Serkan
Askar,
Maciej Ciesielski
2B3 An Integrated Algorithm for Combined Placement and
Libran»
less
.102
Technology Mapping
Yanbin Jiang
Sachin
S.
Sapatnekar
Session 2C: Domino- and ATPG-Based Logic
Synthesis
Moderators: Rajeev Murgai, Fujitsu Labs,
of
America,
Inc., Sunnyvale,
CA;
Massoud Pedram, University of
Southern
California,
Los Angeles,
СА
2C.1 Timing-driven Partitioning for TWo-Phase Domino and Mixed
.107
Static/Domino Implementations
Min
Zhao,
Sachin
S.
Sapatnekar
2C.2 Implication Graph based
Domino
Logic Synthesis
.
Ill
Ki-Wook Kim, C.L. Liu, Sung-Mo Kang
2C3 Synthesis for Multiple Input Wires Replacement of a Gate for
.115
Wiring Consideration
Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu
Session
2Đ:
Electrical and Thermal Analysis
Moderators: Joel R. Phillips, Cadence Design Systems, Inc., San Jose, CA;
Peter
Feldmann,
Bell Labs., Murray Hill, NJ
2D.1 Transient Sensitivity Computation for Transistor Level Analysis
.120
and Tuning
Tuyen VNguyen, PeterR. O'Brien, David Winston
2D.2 An Efficient Method for Hot-spot Identification in ULSI Circuits
.124
Yi-Kan Cheng, Sung-Mo Kang
2DJ A Scalable Substrate Noise Coupling Model for Mixed-Signal ICs,
.128
Anil Samavedam,
Karti
Mayaram,
Terri Fiez
2D.4 Towards True Crosstalk Noise Analysis
.132
Pinhong Chen, Kurt Keutzer
Session
ЗА:
Automatic Test Pattern Generation
Moderators: Janak H.
Patel,
University of Illinois,
Urbana,
IL;
Vamsi
Воррапа,
Fujistu Labs, of America, Sunnyvale, CA
ЗАЛ
SAT Based ATPG Using Fast Justification and Propagation in the
.139
Implication Graph
Paid Tafertshofer, Andreas
Ganz
3A.2 Techniques for Improving the Efficiency of Sequential Circuit
.147
Test Generation
Xijiang Lin, Irith Pomeranz, Sudhakar M. Ready
ЗА
J
Concurrent D-Algorithm on
Reconfigurable
Hardware
.152
Fatih Kocan, Daniel G. Saab
Session 3B: Routing
Moderators: Patrick Groeneveld, Magma Design Automation, Inc.,
Cupertino, CA;
Louis Scheffer, Cadence Design Systems, Inc., San Jose, CA
3B.1 A New Heuristic for Rectilinear
Steiner
Trees
.157
Ion I.
Măndoiu,
Vijay V. Vazirani, Joseph L. Ganley
3B.2 An Implicit Connection Graph Maze Routing Algorithm for ECO Routing
.163
Jason Cong, Jie Fang, Kei-YongKhoo
3B
J
The Associative-Skew Clock Routing Problem
.168
Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky
3B.4 Efficient Incremental Rerouting for Fault Reconfiguration in Field
.173
Programmable Gate Arrays,
Shantanu Dutt, Vimalvel Shanmugavel, Steve Trimberger
Session
ЗС:
Logic-Level Performance Optimization
Moderators: Masahiro Fujita, Fujitsu Labs, of America, Inc., Sunnyvale, CA;
Hamid
Savoj, Magma Design Automation, Inc., Cupertino, CA
3d
Optimal P/N Width Ratio Selection for Standard Cell Libraries
.178
David S.
Kung,
Ruchir
Puri
3C.2 Performance Optimization Under Rise and Fall Parameters
.185
Rajeev Murgai
3C.3 Performance Optimization Using Separator Sets
.191
Yutaka Tamiya
3C.4 Factoring Logic Functions Using Graph Partitioning
.195
Martin C. Golumbic,
Aviad Mintz
Session
3D:
Practical Issues in Order Reduction
Moderators: Luis Miguel
Silveira, INESC, Lisboa,
Portugal;
Tuyen V. Nguyen, IBM Austin Research
Lab.,
Austin,
TX
3D.1 TICER: Realizable Reduction of Extracted RC Circuits
.200
Bernard
N.
Sheehan
3D.2 Realizable Reduction for RC Interconnect Circuits
.204
Anirudh Devgan, Peter R. O'Brien
3D.3 RLC Interconnect Delay Estimation via Moments of Amplitude and
.208
Phase Response
Xiaodong Yang, Walter
H.
Ku, Chung-Kuan Cheng
3D.4 Practical Considerations for Passive Reduction of RLC Circuits
.214
Altan
Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
Session 4A: Embedded Tutorial
Moderator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA
4A.1 Formal Verification Meets Simulation
.221
David L. Dill,
Serdar Tasiran
Session 4B: Embedded Tutorial
Moderator: Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA
4B.1 Interconnect Parasitic Extraction in the Digital
1С
Design Methodology
.223
Mattan
Kamon, Steve McCormick, Kenneth L. Shepard
Session 5A: Timing Optimization
Moderator: Alexander T. Ishii, NEC USA, C&C Research Labs., Princeton, NJ
5A.1 Cycle Time and Slack Optimization for VLSI-Chips
.232
C.
Albrecht,
B. Korte,
J. Schietke, J. Vygen
5A.2
Clock Skew Scheduling for Improved Reliability via Quadratic Programming
. . . 239
Ivan S. Kourtev, Eby G. Friedman
5A3 Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and
. . 244
Redundancy by Timing Graph Manipulation
Chandu Visweswariah, Andrew R. Conn
Session
5В:
Compilation Techniques
for Embedded
Systems
Moderators: Abhijit Ghosh,
Synopsys, Inc., Mountain View, CA;
Donatella Sciuto,
Politecnico di Milano, Milano,
Italy
5B.1
Function Inlining under Code Size Constraints for Embedded Processors
.253
Rainer
Leupers, Peter Marwedel
5B.2 Function Unit Specialization through Code Analysis
.257
Daniel Benyamin, William H. Mangione-Smith
5B3 Lower Bound on Latency for VLIWASIP Datapaths
.261
Margarida
E Jacome,
Gustavo
de Veciana
Session SC: High Level Power Exploration
Moderators: Farid
N.
Najm, University of Toronto, Toronto, Canada;
Kaushik Roy, Purdue University, West Lafayette, IN
5C.1 Interface and Cache Power Exploration for Core-Based Embedded
.270
System Design
Tony D. Givargis,
Jörg Henkel,
Frank Vahid
5C.2 Dynamic Power Management Using Adaptive Learning Tree
.274
Eui-Young Chung,
Luca
Benini,
Giovanni
De Micheli
5C3 Analytical Macromodeling for High-Level Power Estimation
.280
Giuseppe Bemacchia, Marios C. Papaefthymiou
5C.4 Parameterized
RTL
Power Models for Combinational Soft Macros
.284
Alessandro Bugliolo,
Roberto Corgnati, Enrico
Macii,
Massimo
Pancino
Session 5D: Analog and Mixed Signal Test
Moderators: Kwang-Ting (Tim) Cheng, University of California,
Santa Barbara, CA;
Shawn Blanton, Carnegie Mellon University, Pittsburgh, PA
5D.1 Validation and Test Generation for Oscillatory Noise in VLSI Interconnects
. 289
Arani Sinha, Sandeep K. Gupta, Melvin A.
Breuer
5D.2 Fault Modeling and Simulation for Crosstalk in System-on-Chip
.297
Interconnects
Michael Cuviello, Sujit
Dey, Xiaoliang
Bai, Yì
Zhao
5D.3 Robust Optimization Based Backtrace Method for Analog Circuits
.304
Alfred V. Gomes, Abhijit Chatterjee
Session 6A: Globally Untimed Locally Timed Design
Moderators: Kenneth Y. Yun, University of California at San Diego, La
Joüa, CA;
Steven
M.
Nowick, Columbia University, New York, NY
6A.1 A Methodology for Correct-by-Construction Latency Insensitive Design
.309
Luca
P.
Cartoni,
Kenneth L. McMillan, Alexander
Saldanha,
Alberto L. Sangiovanni-Vincentelli
6A.2 What is the cost of Delay Insensitivity
.316
Hiroshi
Saito,
Alex Kondratyev, Jordi Cortadelh, Luciano
Lavagne,
Alexander Yakovlev
6A3 Synthesiser Asynchronous Control Circuits with Automatically Generated
.324
Relative Timing Assumptions
Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken Stevens
6A.4 Direct Synthesis of Timed Asynchronous Circuits
.332
Sung Tae Jung, Chris J. Myers
Session
6В:
Task-Level Analysis and Synthesis
Moderators:
Francky
Catthoor, IMEC,
Leuven,
Belgium;
Stan Liao, Synopsys, Inc., Mountain View, CA
6B.1 Co-Synthesis of Heterogeneous Multiprocessor Systems Using Arbitrated
.339
Communication
David L. Rhodes, Wayne Wolf
6B.2 Power Minimization using System-Level Partitioning of Applications with
.343
Quality of Service Requirements
Gang Qu, Miodrag Potkonjak
6B.3 Worst-Case Analysis of Discrete Systems
.347
Felice Balarin
Session 6C: Floorplanning and Partitioning
Moderators: Naveed Sherwani, Intel Corporation,
Hillsboro,
OR;
D.F. Wong, University of Texas, Austin,
TX
6C.1 Integrated Floorplanning and Interconnect Planning
.354
Hung-Ming Chen,
Hai
Zhou, F.Y. Young, D.F. Wong, Hannah H. Yang, Naveed Sherwani
6C.2 Buffer Block Planning for Interconnect-Driven Floorplanning
.358
Jason Cong, Tianming Kong, David Zhigang Pan
6C.3 A Clustering- and Probability-based Approach for Time-multiplexed
.364
FPGA Partitioning
Mango Chia-Tso
Chao, Guang-Ming
Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
Session 6D: Advances in Model Order Reduction
Moderators: Ibrahim M. Elfadel, IBM Corporation,
Yorktown
Heights, NY;
Alper
Demir, Bell Labs., Murray Hill, NJ
6D.1 The Chebyshev Expansion Based Passive Model for Distributed
.370
Interconnect Networks
Janet M. Wang, Ernest S.
Kuh, Qingjian
Yu
6D.2 Model Reduction for DC Solution of Large Nonlinear Circuits
.376
EmadGad, Michel Nakhla
6D.3 Efficient Model Reduction of Interconnect via Approximate System Gramians
. . . 380
Jing-Rebecca Li, Jacob White
Session 7A: Core Test
Moderators: Srinivas
Patii,
Mentor Graphics Corporation, Austin,
TX;
Nur
A. Touba, University of Texas, Austin,
TX
7A.1 A Framework for Testing Core-Based Systems-on-a-Chip
.385
Srivaths Ravi, Ganesh Lakshminarayana, Niraj
К
Jha
7A.2 Test Scheduling for Core-Based Systems
.391
Krishnendu Chakrabarty
7AJ Partial BIST Insertion to Eliminate Data Correlation
.395
Quishuang Zhang, Ian Harris
Session 7B: Graph Techniques for Design Optimization
Moderators: Sujit
Dey,
University of California at San Diego,
La folla,
CA;
Don MacMillen, Synopsys, Inc., Mountain View, CA
7B.1 A Graph Theoretic Optimal Algorithm for Schedule Compression in
.400
Time-Multiplexed FPGA Partitioning
Huiqun Liu, D.F. Wong
7B.2 Throughput Optimization of General Non-Linear Computations
.406
Inki
Hong, Miodrag Potkonjak, Lisa M.
Guerra
7B.3
Optimal
Allocation
of Carry-Save-Adders in Arithmetic Optimization
.410
Junhyung
Um, Taewhan
Kim, C.L. Liu
7B.4 Regularity Extraction Via Clan-Based Structural Circuit Decomposition
.414
Soha
Hassoun, Carolyn McCreary
Session 7C: Interconnect
Moderators: Jochen
A.G. Jess, Eindhoven University of Technology,
Eindhoven, The Netherlands;
Rajesh K. Gupta, University of California, Irvine, CA
7C.1 Repeater Insertion in Tree Structured Inductive Interconnect
.420
Yehea I. Ismail, Eby G. Friedman, Jose L. Neves
7C.2 Interconnect Scaling Implications for CAD
.425
Ron Ho, Ken Mai, Hema Kapadia, Mark A. Horowitz
7C
3
Is Wire Tapering Worthwhile?
.430
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
Session 7D: Techniques for Parasitic Extraction
Moderators: J. Eric Bracken, Ansoft Corporation, Pittsburgh, PA;
Keith Nabors, Cadence Design Systems, Inc., San Jose, CA
7D.1 Electromagnetic Parasitic Extraction via a Multipole
.437
Method with Hierarchical Refinement
Michael W. Beattie, Lawrence T. Pileggi
7D.2 Virtual Screening: A Step Towards a Sparse Partial Inductance Matrix
.445
A.J.
Dammers,
N.P. van derMeijs
7D.3 A Wide Frequency Range Surface Integral Formulation for
.453
3-D
RLC Extraction
/.
Wang, J.
Tausch,
J. White
Session 8A: Embedded Tutorial
Moderator: Lawrence T. Pileggi, Carnegie Mellon University,
Pittsburgh, PA
8A.1 SOI Technology and Tools
.459
SaniR. Nassif, Tuyen V Nguyen
Session 8B: Embedded Tutorial
Moderator: Rolf Ernst, Technical University of Braunschweig,
Braunschweig, Germany
8B.1 System Level Design and Debug of High-Performance Embedded Media
.461
Systems
Kees
A.
Vissers,
Pieter
van
der Wolf, Gert-Jan
van Rootselaar
Session 9A: Test Pattern Analysis
Moderators: Robert Aitken, Hewlett-Packard Company, Palo Alto, CA;
Sreejit Chakravarty, Intel Corporation, Santa Clara, CA
9A.1 An Approach for Improving the Levels of Compaction Achieved by
.463
Vector Omission
Irith Pomeranz, Sudhakar M. Ready
9A.2 Deep
Submicron
Defect Detection with the Energy Consumption Ratio
.467
Bapiraju Vinnakota
9A3 Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits
.471
Panka¡
Pant, Abhijit Chatteqee
Session
9В:
Memory
and Interconnect Optimization in
High Level Synthesis
Moderator: Kazutoshi Wakabayashi, NEC Corporation, Kawasaki, Japan
9B.1 Memory Bank Customization and Assignment in Behavioral Synthesis
.477
Preeti Ranjan Panda
9B.2 Memory Binding for Performance Optimization of Control-Flow
.482
Intensive Behaviors
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
9B.3 Improved Interconnect Sharing by Identity Operation Insertion
.489
Dirk Herrmann, Rolf Ernst
Session 9C: System Verification
Moderators: Mandayam Srivas, SRI International, Menlo Park, CA;
Pei-Hsin Ho, Synopsys, Inc., Beaverton, OR
9C.1 Formal Specification and Verification of a Dataflow Processor Array
.494
Thomas A. Henzinger, Xiaojun Liu, Shaz Qadeer, Sriram K. Rajamani
9C.2 Distributed Simulation of VLSI Systems via Looka head-Free
.500
Self-Adaptive Optimistic and Conservative Synchronization
Dragos
Lungeanu, C.-J. Richard Shi
9C.3 Synchronous Equivalence for Embedded Systems: A Tool for
.505
Design Exploration
Harry Hsieh, Felice Balarin, Alberto L. Sangiovanni-Vincentelli, Luciano
Lavagne
Session 9D: Fanout Optimization
Moderators: Yuji Kukimoto, Monterey Design Systems, Inc., Sunnyvale, CA;
Shih-Chieh Chang, National Chung-Cheng University, Taiwan, ROC
9D.1 On the Global Fanout Optimization Problem
.511
Rajeev Murgai
9D.2 LEOPARD: A Logical Effort-based fanout Optimizer for ARea and Delay
.516
Peyman Rezvani, AmirH. Ajami, Massoud Pedram,
Hamid
Savoj
9D.3 Optimum Loading Dispersion for High-Speed Tree-Type Decision Circuitry
. 520
lie-Hong Roland Jiang, Iris Hui-Ru Jiang
Session 10A: Timing Analysis
Moderators: David J. Hathaway, IBM Corporation, Essex Junction, VT;
Joao P. Marques
Silva,
Technical University of Lisbon,
Lisboa,
Portugal
10A.1 Symbolic Functional and Timing Verification of Transistor-Level Circuits
.526
Clayton B. McDonald, Randal E. Bryant
10A.2 Body-Voltage Estimation in Digital PD-SOI Circuits and its Application
.531
to Static Timing Analysis
Kenneth L. Shepard, Dae-Jin Kim
10A.3 Functional Timing Optimization
.539
Alexander
Saldanha
10A.4 Timing-Safe False Path Removal for Combinational Modules
.544
Yuji Kukimoto, Robert K. Brayton
Session ÎOB:
Concurrency in Embedded Systems
Moderators: Joseph Buck, Synopsys, Inc., Mountain View, CA;
Wayne Wolf, Princeton University, Princeton, NJ
10B.1 JMTP: An Architecture for Exploiting Concurrency in Embedded Java
.551
Applications with Real-Time Considerations
Rachid Helaihel, Kunle Olukotun
10B.2 FunState
-
An Internal Design Representation for Codesign
.558
L.
Thiele,
К.
Strehi,
Dirk Ziegenbein, Rolf Ernst, J. Teich
10B.3 Fast Performance
Analysis of Bus-Based
System-On-Chip.566
Communication Architectures
Kanishka Lahiri, Anand Raghunathan,
Sufit
Dey
Session IOC: Semi-Formal Verification
Moderator: Thomas R. Shiple, Synopsys, Inc., Mountain View, CA;
Alan
Ни,
The University of British Columbia, Vancouver, Canada
10C.1 Probabilistic State Space Search
.574
Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton
IOC.
2
Improving Coverage Analysis and Test Generation for Large Designs
.580
Jules P.
Bergmann, Mark
A. Horowitz
10C3 Modeling Design Constraints and Biasing in Simulation Using BDDs
.584
Jun
Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
Session 10D: Intellectual Property Protection
Moderators:
Emil S.
Ochotta, Xilinx, Inc., San Jose, CA;
Margarida
Jacome, University of Texas, Austin,
TX
10D.1 Copyright Protection of Designs Based on
Multi
Source IPs
.591
Edoardo
Charbon,
líhami Torunoglu
10D.2 Localized Watermarking: Methodology and Application to Operation Scheduling
. 596
Darko Kirovski, Miodrag Potkonjak
lODJ Copy Detection for Intellectual Property Protection of VLSI Designs
.600
Andrew B. Kahng, Darko Kirovski,
Stefanus Mantik,
Miodrag Potkonjak, Jennifer L. Wong
Session
11
A: Embedded Tutorial
Moderator: Jacob K. White, Massachusetts Institute of Technology,
Cambridge, MA
11A.1 Path Toward Future CAD Environments for MEMS
.606
Gary K. Fedder,
Tamal
Микпецее
Session 11B: ICCAJtylSSS Invited Papers
Moderator: NikilDutt, University of California, Irvine, CA
11B.1 Design of a Set-Top Box System on a Chip
.608
Eric Foster
11B.2 On the Rapid Prototyping and Design of a Wireless Communication
.609
System on a Chip
Brian Kelley
Session 12A:
Embedded
Tutorial
Moderator: Jacob K.
White, Massachusetts
Institute
of
Technology,
Cambridge,
MA
12A.1
Advances in
Transistor
Timing,
Simulation,
and Optimization
.611
Jacob Avidan,
Abe
Elfadel, D.E
Wong
Session 12B:
Joint ICCAD / ISSS Session
Embedded
Tutorial
Moderator: Reinaldo
Bergamaschi, IBM
Corporation, Yorktown
Heights, NY
12B.1
Embedded Java: Techniques and Applications
.613
Brian Barry, John Duimovich |
| any_adam_object | 1 |
| author_corporate | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
| author_corporate_role | aut |
| author_facet | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
| author_sort | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) San José, Calif |
| building | Verbundindex |
| bvnumber | BV012865861 |
| classification_rvk | SS 1999 |
| classification_tum | DAT 810f |
| ctrlnum | (OCoLC)313763931 (DE-599)BVBBV012865861 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1999 San Jose Calif. gnd-content |
| genre_facet | Konferenzschrift 1999 San Jose Calif. |
| id | DE-604.BV012865861 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:23:37Z |
| institution | BVB |
| institution_GND | (DE-588)10006144-8 |
| isbn | 0780358325 0780358333 0780358341 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008755437 |
| oclc_num | 313763931 |
| open_access_boolean | |
| owner | DE-739 DE-20 DE-91G DE-BY-TUM DE-706 |
| owner_facet | DE-739 DE-20 DE-91G DE-BY-TUM DE-706 |
| physical | XXIV, 613 S. Ill., graph. Darst. |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | ACM [u.a.] |
| record_format | marc |
| spelling | International Conference on Computer Aided Design (Institute of Electrical and Electronics Engineers) 1999 San José, Calif. Verfasser (DE-588)10006144-8 aut Digest of technical papers November 7 - 11, 1999, San Jose, California 1999 IEEE/ACM International Conference on Computer-Aided Design ICCAD 99 Proceeding of the 1999 International Conference on Computer-Aided Design IEEE ACM digest of technical papers New York ACM [u.a.] 1999 XXIV, 613 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Konsumelektronik (DE-588)4165117-0 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1999 San Jose Calif. gnd-content VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s CAD (DE-588)4069794-0 s 1\p DE-604 Layout Mikroelektronik (DE-588)4264372-7 s 2\p DE-604 Integrierte Schaltung (DE-588)4027242-4 s 3\p DE-604 Logische Schaltung (DE-588)4131023-8 s 4\p DE-604 Konsumelektronik (DE-588)4165117-0 s 5\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008755437&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Digest of technical papers November 7 - 11, 1999, San Jose, California Logische Schaltung (DE-588)4131023-8 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Konsumelektronik (DE-588)4165117-0 gnd Entwurf (DE-588)4121208-3 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4027242-4 (DE-588)4264372-7 (DE-588)4165117-0 (DE-588)4121208-3 (DE-588)4069794-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Digest of technical papers November 7 - 11, 1999, San Jose, California |
| title_alt | ICCAD 99 Proceeding of the 1999 International Conference on Computer-Aided Design IEEE ACM digest of technical papers |
| title_auth | Digest of technical papers November 7 - 11, 1999, San Jose, California |
| title_exact_search | Digest of technical papers November 7 - 11, 1999, San Jose, California |
| title_full | Digest of technical papers November 7 - 11, 1999, San Jose, California 1999 IEEE/ACM International Conference on Computer-Aided Design |
| title_fullStr | Digest of technical papers November 7 - 11, 1999, San Jose, California 1999 IEEE/ACM International Conference on Computer-Aided Design |
| title_full_unstemmed | Digest of technical papers November 7 - 11, 1999, San Jose, California 1999 IEEE/ACM International Conference on Computer-Aided Design |
| title_short | Digest of technical papers |
| title_sort | digest of technical papers november 7 11 1999 san jose california |
| title_sub | November 7 - 11, 1999, San Jose, California |
| topic | Logische Schaltung (DE-588)4131023-8 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Konsumelektronik (DE-588)4165117-0 gnd Entwurf (DE-588)4121208-3 gnd CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Logische Schaltung Integrierte Schaltung Layout Mikroelektronik Konsumelektronik Entwurf CAD VLSI Konferenzschrift 1999 San Jose Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008755437&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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