Proceedings: ISPD-99 ; Monterey, CA, April 12 - 14, 1999
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York
ACM
1999
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | IX, 223 S. graph. Darst. |
| ISBN: | 1581130899 |
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| 111 | 2 | |a International Symposium on Physical Design |n 3 |d 1999 |c Monterey, Calif. |j Verfasser |0 (DE-588)5340232-7 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b ISPD-99 ; Monterey, CA, April 12 - 14, 1999 |c 1999 International Symposium on Physical Design |
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| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
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| 650 | 4 | |a Integrated circuits |x Design and construction |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |v Congresses | |
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Datensatz im Suchindex
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| adam_text | Table
of
Contents
Foreword
............................................................................................................
iv
Symposium
Organization
.........................................................................................
v
Table of Contents
..................................................................................................
™
Session
1.0:
Welcome and Keynote Address
Moderator: Dwight Hill (Synopsys)
•
Welcome to ISPD-99
....................................................................................................................1
D.F. Wong (UT-Austin)
•
Tales From the Trenches
С
Malachowski (nVidia)
Session
1.1:
Tutorial on Clocks
Moderator:
Sachin
Sapatnekar (U. Minnesota)
•
Challenges in Clock Distribution Networks
..........................................................................................2
Eby Friedman, Niraj Bindal (U. Rochester, Intel)
Session
1.2:
Tutorial on Noise
Moderator: Manfred
Wiesel
(Intel)
•
The Deep Sub-micron Signal Integrity Challenge
...................................................................................3
D. Kirkpatrick (Intel)
Session
13:
Analog Design and Signal Analysis
Moderator: C.K. Cheng (UCSD)
•
Methodology to Analyze Power, Voltage Drop and Their Effects on Clock Skew/Delay in Early Stages of Design
......9
M. Iwabuchi,
N.
Sakamoto, Y.
Selcine, T.
Omachi (Hitachi)
•
EMI-Noise Analysis Under ASIC Design Environment
...........................................................................16
5.
Hayashi, M.I. Yamada (Toshiba)
•
An Efficient Sequential Quadratic Programming Formulation of Optimal Wire Spacing for Cross-Talk Noise
Avoidance Routing
......................................................................... 22
P.Morton.W.Dai(UCSC)
Session 1.4: Posters
on Timing and Circuits
Moderator: Rob
Rutenbar
(CMU)
•
Post -Routing Timing Optimization with Routing Characterization
..............................................................30
С
Changfan, Y.-C. Hsu, F.-S. Tsai
(Avant!)
•
Buffer Insertion for Clock Delay and Skew Minimization
.........................................................................36
X.
Zeng,
D.Zhou, W. Li (Fudan U.,
UNC)
•
Incremental Capacitance Extraction and its Application to Iterative Timing Driven Detailed Routing
.....................42
Y. Yuan, P. Banerjee (Northwestern U.)
•
Interconnect Coupling Noise in CMOS VSLI Circuits
............................................................................48
K. Tang, E. Friedman (U. Rochester)
Session
1.5:
Panel: SCR Physical Design Top Ten Problems
Moderator: Chuck Alpert (IBM)
•
SRC Top Ten Physical Design Problems
............................................................................................55
J. Parkhurst,
N.
Sherwani, S.
Maturi,
D.
Ahrams,
E. Chiprout (Intel, LSI Logic Corp., National
Semiconductor,
IBM)
Session
2:
Benchmarks
Moderator:
Jochen
Jess
(Eindhoven)
•
Towards Synthetic Benchmark Circuits for Evaluating Timing-Driven CAD Tools
..........................................60
D. Stroobandt, P.I Verplaetse, J. Van Campenhout (U
.
Ghent)
•
Generation of Very Large Circuits to Benchmark the Partitioning of FPGA s
..................................................67
J. Pistorius,
E. Legai,
M. Minoux
(Mentor, Pierre
et
Marie Curie)
•
Transistor-Level Micro Placement and Routing for Two-Dimensional Digital VLSI Cell Synthesis
.......................74
M. Riepe,
K. Sakallah
(U. Michigan)
Session
2.1:
Partitioning, Placement, and Floorplanning
Moderator: Massoud Pedram
(USC)
•
Partitioning by Iterative Deletion
...................................................................................................83
P.H. Madden
(SUNY)
•
Optimal Partitioners and End-Case Placers for Standard-Cell Layout
...........................................................90
A.E. Caldwell,
A.B.
Kahng, B.I.L. Markov (UCLA)
•
Slicing Floorplans with Range Constraints
.........................................................................................97
F.Y. Young, D.F. Wong (UT-Austin)
•
Arbitrary
Convex
and Concave
Rectilinear
Block
Packing
......................................................................103
К.
Fujiyosi,
H.
Murata (Tokyo
U.)
Session
2.2:
Tutorial on Manufacturing
Moderator: Andrew Kahng (UCLA)
•
Subwavelength Optical Lithography: Challenges and Impact on Physical Design
...........................................112
A.B.
Kahng, Y.C..
Pati
(UCLA, Numeric Technologies)
Session
2.3:
Sizing and Buffering, Plus Lithography
Moderator: Jason Cong (UCLA)
•
Optimal Phase Conflict Removal for Layout of Dark Field Alternating Phase Shifting Masks
...........................121
P. Berman,
A.B.
Kahng, D. Vidhani,
E.H.
Wang, F.A.
Zelikovsky (UCLA, Penn State, Georgia State)
•
Gate Sizing with Controlled Displacement
.......................................................................................127
W. Chen, C.-T. Hsieh, M. Pedram
(USC)
•
Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI Interconnect Under a Higher Order AWE Model
..........................................................................................................................................133
J.
Ни,
S.
Sapatnekar
(U.
of Minnesota)
Session
2.4:
Posters on Placement and Partitioning
Moderator:
Carl Sechen
(U.
Washington)
•
Efficient Solution of Systems of Orientation Constraints
.....................................................................140
J. Ganley (Cadence)
•
Behavior of Congestion Minimization During Placement
....................................................................145
M. Wang, M. Sarrafzadeh (Northwestern U.)
•
Partitioning with Terminals: A New Problem and New Benchmarks
.......................................................151
C. Alpen,
A. Caldwell,
A.B.
Kahng, I. Markov (UCLA and IBM)
•
Transistor-Level Placement for Full Custom Datapath Cell Design
...................................... 158
D. Vahia, M.
Ciesielski (U.
Mass)
•
Circuit Clustering Using Graph Coloring
....................................................................................164
A. Singh, M.Marek-SadowskaiUCSB)
Session
2.5:
Dinner Talk
Moderator: Martin Wong (UT-Austin)
•
Why So Many Start-ups Today? A Designer and Venture Capitalist s View
................................................170
A. Bechtolsheim (Silicon Valley)
Vili
Session 3.0:
Thermal
and
MCM
Moderator: Naveed Sherwani (Intel)
•
Interconnect Thermal Modeling for Determining Design Limits on Current Density
...................................172
D. Chen, E. Li, E.
Rosenbaum,
S.-M.
Kang
(U.
Illinois)
•
Standard Cell Placement for Even On-Chip Thermal Distribution
.........................................................179
C.-H. Tsai, S.-M. Kang (U. Illinois)
Session
3.1:
Global Routing
Moderator: Patrick Groeneveld (Magma)
•
Measuring Nets Routability for MCM s General Area Routing Problems
.................................................186
Kusnadi, J.D. Carothers (U. Arizona)
•
Getting to the Bottom of
DSM
II: The Global Wiring Paradigm
...........................................................193
D. Sylvester, K. Keutzer (U. Berkeley)
•
Crosstalk Constrained Global Route Embedding
..............................................................................201
P. Parakh, R.B. Brown (U. Michigan)
Session
3.2:
Routing
Moderator: Ren-Song Tsay (Axis)
•
Timing Driven Maze Routing
....................................................................................................208
S.-W.
Hur,
A. Jagannathan, J.
Ullis
(U.
Illinois at Chicago)
•
Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms
...............................................214
/.
Cong, J. Fang, K.-Y. Khoo (UCLA)
Session
33:
Panel Physical Synthesis
Moderator: Wayne Dai (UCSC)
•
Layout Driven Synthesis or Synthesis Driven Layout?
.......................................................................221
W. Dai (UCSC)
Author Index
........................................................................................................................222
ix
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| spelling | International Symposium on Physical Design 3 1999 Monterey, Calif. Verfasser (DE-588)5340232-7 aut Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 1999 International Symposium on Physical Design ISPD-98 New York ACM 1999 IX, 223 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Design and construction Congresses Integrated circuits Very large scale integration Congresses VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1999 Monterey Calif. gnd-content VLSI (DE-588)4117388-0 s CAD (DE-588)4069794-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008562992&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 Integrated circuits Design and construction Congresses Integrated circuits Very large scale integration Congresses VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)1071861417 |
| title | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 |
| title_alt | ISPD-98 |
| title_auth | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 |
| title_exact_search | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 |
| title_full | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 1999 International Symposium on Physical Design |
| title_fullStr | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 1999 International Symposium on Physical Design |
| title_full_unstemmed | Proceedings ISPD-99 ; Monterey, CA, April 12 - 14, 1999 1999 International Symposium on Physical Design |
| title_short | Proceedings |
| title_sort | proceedings ispd 99 monterey ca april 12 14 1999 |
| title_sub | ISPD-99 ; Monterey, CA, April 12 - 14, 1999 |
| topic | Integrated circuits Design and construction Congresses Integrated circuits Very large scale integration Congresses VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Integrated circuits Design and construction Congresses Integrated circuits Very large scale integration Congresses VLSI CAD Konferenzschrift 1999 Monterey Calif. |
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