Holdings: Parallel VLSI neural system design

Parallel VLSI neural system design:

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Bibliographic Details
Main Author:	Zhang, David 1949- (Author)
Format:	Book
Language:	English
Published:	Singapore [u.a.] Springer 1999
Subjects:	Integrated circuits > Very large scale integration Neural networks (Computer science) Parallel processing (Electronic computers) Mustererkennung Entwurf Neuronales Netz Entwurfsautomation VLSI
Online Access:	Inhaltsverzeichnis
Item Description:	Literaturverz. S. 235 - 252
Physical Description:	XIII, 257 S. Ill., graph. Darst.
ISBN:	9813083301

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MARC


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Record in the Search Index

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adam_text	PARALLEL VLSI NEURAL SYSTEM DESIGN DAVID ZHANG SPRINGER CONTENTS PREFACE V CHAPTER 1 VLSI NEURAL SYSTEM DESIGN METHODOLOGY 1 1.1 INTRODUCTION 1 1.2 NEURAL NETWORK MODELS... 3 1.2.1 BIOLOGICAL NEURAL NETWORKS 3 1.2.2 ARTIFICIAL NEURAL NETWORKS 6 1.3 ANN ARCHITECTURES 10 1.4 HARDWARE IMPLEMENTATIONS 11 1.4.1 ANALOG AND MIXED IMPLEMENTATIONS 12 1.4.2 DIGITAL IMPLEMENTATIONS 13 1.5 VLSI SYSTEM DESIGN METHODOLOGY 14 PARTI PARALLEL ANN MODELS 21 CHAPTER 2 AN UNSUPERVISED LEARNING MODEL 23 2.1 INTRODUCTION 23 2.2 FUZZY CLUSTERING NEURAL NETWORKS ..28 2.2.1 NETWORK ARCHITECTURE 28 2.2.2 LEARNING ALGORITHM 28 2.3 PARALLEL FCNN MODEL 32 2.4 EXPERIMENTAL RESULTS 32 2.5 SUMMARY 40 CHAPTER 3 A SUPERVISED TRAINING MODEL 41 3.1 INTRODUCTION 41 3.2 LINEAR SEPARABILITY ANALYSIS 44 3.2.1 DEFINITIONS 44 3.2.2 LAYERED PERCEPTRONS 46 PARALLEL VLSI NEURAL SYSTEM DESIGN 3.3 LAYER ADAPTATION APPROACH 48 3.3.1 LINEAR SEPARABILITY PRINCIPLE 49 3.3.2 ADAPTATION APPROACH 50 3.4 EXPERIMENT: PATTERN RECOGNITION 53 3.5 COMPARISONS 55 3.6 SUMMARY 57 CHAPTER 4 A NEURAL-LIKE NETWORK MODEL 59 4.1 INTRODUCTION 59 4.1.1 NOTATION 60 4.1.2 RESIDUE NUMBER SYSTEM (RNS) 61 4.1.3 NEURAL NETWORK ARCHITECTURE 61 4.2 FRNN COMPUTING MODEL 63 4.3 FRNN ARCHITECTURE 66 4.4 CASE STUDIES 67 4.4.1 A MULTIPLIER 68 4.4.2 RNS TO BINARY CONVERTER 69 4.5 SUMMARY 70 PART II VLSI ARCHITECTURES 71 CHAPTER 5 MAPPING ANN ONTO SYSTOLIC ARRAYS 73 5.1 INTRODUCTION 73 5.1.1 SYSTOLIC ARRAYS 74 5.1.2 MAPPING ALGORITHM TO SYSTOLIC ARCHITECTURE77 5.2 MAPPING POLICIES 79 5.3 DESIGN APPROACH 82 5.3.1 TYPICAL SA STRUCTURES 82 5.3.2 PIPELINE MATCHING 84 5.3.3 ITERATION PROCESSING 84 5.4 CASE STUDY 86 5.4.1 HAMMING NET 86 5.4.2 SIMULATIONS AND EXPERIMENTS 90 5.5 SUMMARY 91 CONTENTS XI CHAPTER 6 CHAPTER 7 CHAPTER 8 A PARALLEL ARCHITECTURE IMPLEMENTED BY SYSTOLIC ARRAYS 9 3 6.1 INTRODUCTION 93 6.2 FCNN ARCHITECTURE 94 6.3 PERFORMANCE ANALYSIS 96 6.4 MAPPING FCNN ONTO SA 100 6.5 SUMMARY 106 A PIPELINED ARCHITECTURE BASED ON WINDOW OPERATION 107 7.1 INTRODUCTION 107 7.2 PIPELINED ARCHITECTURE 109 7.2.1 WINDOW MODEL 109 7.2.2 PIPELINED ARCHITECTURE 111 7.2.3 BUILDING UNIT DESIGN 112 7.3 WINDOW IMPLEMENTATION 116 7.3.1 PARALLEL DATA FLOW WINDOW 116 7.3.2 SERIAL DATA FLOW WINDOW 117 7.3.3 WINDOW COMPUTATION ELEMENT 118 7.4 CASE STUDIES 120 7.5 PERFORMANCE ANALYSIS 126 7.6 SUMMARY 129 A SIMPLIFIED ARCHITECTURE USING A PRIORI KNOWLEDGE 131 8.1 INTRODUCTION 131 8.2 TYPICAL STRUCTURE MODELS 133 8.2.1 OUTPUT ROM MODEL 133 8.2.2 INPUT ROM MODEL 135 8.2.3 LEARNING ROM MODEL 135 8.3 ROM LAYER IN VLSI 136 8.4 EXAMPLES 136 8.5 SUMMARY 147 XLL PARALLEL VLSI NEURAL SYSTEM DESIGN PART III HARDWARE IMPLEMENTATIONS 149 CHAPTER 9 COMPUTATIONAL BLOCKS DESIGN FOR DIGITAL ANN . 151 9.1 INTRODUCTION 151 9.2 PIPELINED SWITCHING TREES 152 9.3 GRAPH BASED REDUCTION 153 9.3.1 GRAPH REDUCTION RULES 154 9.3.2 MINIMIZATION CONSIDERATIONS 157 9.3.3 EXAMPLE RESULTS 159 9.4 CIRCUIT CONSIDERATIONS 161 9.4.1 WORST CASE TEST 161 9.4.2 REDUCTION OF CHARGE SHARING 162 9.4.3 REDUCTION OF TREE HEIGHT 165 9.4.4 TRANSISTOR SIZING 169 9.5 PRELIMINARY FABRICATION RESULTS 170 9.6 SUMMARY 171 CHAPTER 10 DIGITAL ANN COMPRESSOR DESIGN 173 10.1 INTRODUCTION 173 10.2 C 2 PLMODEL 175 10.3 3-2 COMPRESSOR DESIGN 176 10.3.1 BASIC STRUCTURE 177 10.3.2 COMPARISON WITH CPL 181 10.4 DNN APPLICATIONS 183 10.5 SUMMARY 189 CHAPTER 11 HYBRID PROGRAMMABLE ANN DESIGN 191 11.1 INTRODUCTION 191 11.2 ANALYSIS AND DESIGN FOR PRNN 193 11.3 IMPROVED PRNN CIRCUIT 197 11.3.1 SYNAPSE BUILDING BLOCK 197 11.3.2 NEURON BUILDING BLOCK 199 11.3.3 CONNECTION NETWORK 201 CONTENTS 11.4 EXPERIMENTAL RESULTS 201 11.5 SUMMARY 203 APPENDIX A 203 CHAPTER 12 VLSI IMPLEMENTATION FOR FINITE RING ANN. 207 12.1 INTRODUCTION 207 12.2 FRRR ARCHITECTURE 208 12.2.1 MODULO REDUCTION 208 12.2.2 MSB CARRY ITERATION 209 12.2.3 FEEDFORWARD PROCESSING 212 12.3 VLSI IMPLEMENTATION 213 12.3.1 CARRY LOOK-AHEAD ADDER 214 12.3.2 ROM IMPLEMENTATION 216 12.3.3 ROM LOGIC CELL 217 12.4 COMPARISON 218 12.5 SUMMARY 223 APPENDIX B 225 CHAPTER 13 CONCLUSIONS AND PROSPECTS 227 BIBLIOGRAPHY 235 INDEX 253
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author	Zhang, David 1949-
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spelling	Zhang, David 1949- Verfasser (DE-588)12099190X aut Parallel VLSI neural system design David Zhang Singapore [u.a.] Springer 1999 XIII, 257 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturverz. S. 235 - 252 Integrated circuits Very large scale integration Neural networks (Computer science) Parallel processing (Electronic computers) Mustererkennung (DE-588)4040936-3 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Neuronales Netz (DE-588)4226127-2 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Mustererkennung (DE-588)4040936-3 s Neuronales Netz (DE-588)4226127-2 s VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s DE-604 Entwurf (DE-588)4121208-3 s GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008526229&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Zhang, David 1949- Parallel VLSI neural system design Integrated circuits Very large scale integration Neural networks (Computer science) Parallel processing (Electronic computers) Mustererkennung (DE-588)4040936-3 gnd Entwurf (DE-588)4121208-3 gnd Neuronales Netz (DE-588)4226127-2 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd
subject_GND	(DE-588)4040936-3 (DE-588)4121208-3 (DE-588)4226127-2 (DE-588)4312536-0 (DE-588)4117388-0
title	Parallel VLSI neural system design
title_auth	Parallel VLSI neural system design
title_exact_search	Parallel VLSI neural system design
title_full	Parallel VLSI neural system design David Zhang
title_fullStr	Parallel VLSI neural system design David Zhang
title_full_unstemmed	Parallel VLSI neural system design David Zhang
title_short	Parallel VLSI neural system design
title_sort	parallel vlsi neural system design
topic	Integrated circuits Very large scale integration Neural networks (Computer science) Parallel processing (Electronic computers) Mustererkennung (DE-588)4040936-3 gnd Entwurf (DE-588)4121208-3 gnd Neuronales Netz (DE-588)4226127-2 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd
topic_facet	Integrated circuits Very large scale integration Neural networks (Computer science) Parallel processing (Electronic computers) Mustererkennung Entwurf Neuronales Netz Entwurfsautomation VLSI
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008526229&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT zhangdavid parallelvlsineuralsystemdesign

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