Genetic algorithms for VLSI design, layout & test automation: [the complete guide to VLSI design with genetic algorithms]
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ
Prentice Hall
1999
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIII, 338 S. graph. Darst. |
| ISBN: | 0130115665 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV012490900 | ||
| 003 | DE-604 | ||
| 005 | 20060607 | ||
| 007 | t | ||
| 008 | 990408s1999 d||| |||| 00||| eng d | ||
| 020 | |a 0130115665 |9 0-13-011566-5 | ||
| 035 | |a (OCoLC)313311779 | ||
| 035 | |a (DE-599)BVBBV012490900 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-29T |a DE-91 |a DE-703 |a DE-706 | ||
| 082 | 0 | |a 621.39/5 | |
| 082 | 0 | |a 621.395 | |
| 084 | |a ST 285 |0 (DE-625)143648: |2 rvk | ||
| 084 | |a ST 301 |0 (DE-625)143651: |2 rvk | ||
| 084 | |a MAT 919f |2 stub | ||
| 084 | |a ELT 272f |2 stub | ||
| 100 | 1 | |a Mazumder, Pinaki |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Genetic algorithms for VLSI design, layout & test automation |b [the complete guide to VLSI design with genetic algorithms] |c Pinaki Mazumder ; Elizabeth M. Rudnick |
| 264 | 1 | |a Upper Saddle River, NJ |b Prentice Hall |c 1999 | |
| 300 | |a XIII, 338 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Genetic algorithms | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Testing | |
| 650 | 0 | 7 | |a Genetischer Algorithmus |0 (DE-588)4265092-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Genetischer Algorithmus |0 (DE-588)4265092-6 |D s |
| 689 | 0 | 1 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 2 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Rudnick, Elisabeth M. |e Verfasser |4 aut | |
| 856 | 4 | 2 | |m HBZ Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008478990&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-008478990 | ||
Datensatz im Suchindex
| _version_ | 1804127134566842368 |
|---|---|
| adam_text | CONTENTS
PREFACE xi
1 INTRODUCTION 1
1.1 Introduction to GA Terminology 3
1.2 The Simple GA 5
1.3 The Steady State Algorithm 7
1.4 Genetic Operators 9
1.4.1 Selection 9
1.4.2 Crossover 10
1.4.3 Mutation 12
1.4.4 Fitness Scaling 13
1.4.5 Inversion 14
1.5 GA Example 16
1.6 GAs for VLSI Design, Layout, and Test Automation 18
1.6.1 Partitioning 20
1.6.2 Automatic Placement 22
1.6.3 Automatic Routing 26
1.6.4 Technology Mapping for FPGAs 30
1.6.5 Automatic Test Generation 32
1.6.6 Power Estimation 34
2 PARTITIONING 37
2.1 Problem Description 38
2.1.1 Partitioning Algorithms 41
2.1.2 Taxonomy of Partitioning Algorithms 42
2.2 Circuit Partitioning by Genetic Algorithm 46
v
vi
2.2.1 Incorporation and Duplicate Check 52
2.2.2 Mutation 53
2.2.3 Genetic Multiway Partitioning 55
2.2.4 Evaluation 56
2.2.5 Results 58
2.3 Hybrid Genetic Algorithm for Ratio Cut Partitioning 60
2.3.1 Genetic Encoding 61
2.3.2 Selection, Crossover, and Mutation 61
2.3.3 Local Improvement 62
2.3.4 Preprocessing 64
2.3.5 Weighted DFS Reordering (WDFR) 64
2.3.6 Time Complexity 65
2.3.7 Results 65
2.3.8 Comparison of GA with Other Methods 66
2.4 Conclusion 67
3 STANDARD CELL AND MACRO CELL PLACEMENT 69
3.1 Standard Cell Placement 71
3.1.1 GASP Algorithm 72
3.1.2 Crossover Operators 76
3.1.3 Optimizing the Genetic Algorithm 78
3.1.4 Comparison with Simulated Annealing 80
3.1.5 Experimental Results 81
3.2 Macro Cell Placement 85
3.2.1 Unified Algorithm 87
3.2.2 Application to Macro Cell Placement 90
3.2.3 Experimental Results 98
3.2.4 Limitations and Enhancements 104
4 MACRO CELL ROUTING 107
4.1 The Steiner Problem in a Graph 109
4.1.1 Problem Definition 110
4.1.2 Description of the Algorithm 111
4.1.3 Experimental Method 118
4.1.4 Results 121
4.1.5 Summary and Conclusion 134
4.2 Macro Cell Global Routing 135
4.2.1 Routing Phase I : Applying the GA for the SPG 135
vii
4.2.2 Routing Phase II : Minimizing Layout Area 136
4.2.3 Experimental Results 137
4.2.4 Summary and Conclusion 138
5 FPGA TECHNOLOGY MAPPING 140
5.1 Problem Description 141
5.2 Circuit Segmentation and FPGA Mapping 143
5.2.1 TLU Based FPGA Architecture 143
5.2.2 Mapping Using Circuit Segmentation 146
5.3 Circuit Segmentation for Pseudo Exhaustive Testing 150
5.4 Experimental Results 151
5.4.1 Results for FPGA Technology Mapping 151
5.4.2 Experimental Results of Segmentation for PET 154
5.5 Summary 156
6 AUTOMATIC TEST GENERATION 158
6.1 Problem Description 160
6.2 Test Generation in a GA Framework 165
6.2.1 Encoding Alphabet 167
6.2.2 GA Parameters 168
6.2.3 Fitness Function 168
6.2.4 An Implementation 171
6.2.5 Evaluation of GA Parameters 174
6.3 Test Generation for Test Application Time Reduction 178
6.4 Deterministic/Genetic Test Generator Hybrids 184
6.4.1 GA HITEC Hybrid 186
6.4.2 ALT TEST Hybrid 190
6.5 Use of Finite State Machine Sequences 199
6.5.1 Algorithm Overview 201
6.5.2 Single Time Frame Mode 206
6.5.3 Test Generation Procedure 207
6.5.4 Experimental Results 210
6.6 Dynamic Test Sequence Compaction 212
6.6.1 Overview 214
6.6.2 Experimental Results 218
6.7 Conclusions 224
viii
7 PEAK POWER ESTIMATION 227
7.1 Problem Description 229
7.1.1 Adding Delay Models to the Problem 232
7.2 Application of Genetic Algorithms to Peak Power Estimation 234
7.3 Estimation of Peak Single Cycle and n Cycle Powers 235
7.3.1 Resolving the Problem of State Reachability 236
7.4 Peak Sustainable Power Estimation 237
7.5 Experimental Results 239
7.6 Summary 249
8 PARALLEL IMPLEMENTATIONS 252
8.1 Wolverines: Standard Cell Placement on a Network of Workstations 254
8.1.1 Standard Cell Placement Using the Genetic Algorithm 255
8.1.2 Analysis of Serial Algorithm 258
8.1.3 Distributed Placement Algorithm 259
8.1.4 Experimental Results 264
8.1.5 Conclusions 280
8.2 Parallel Genetic Algorithms for Automatic Test Generation 280
8.2.1 Sequential GA Based ATG 281
8.2.2 Parallel GA Based ATG 284
8.2.3 Experimental Results 288
8.2.4 Conclusions 293
9 CONCLUSION 295
9.1 Problem Encoding 296
9.2 Fitness Function 297
9.3 Type of GA 298
9.4 GA Parameters 298
9.5 Genetic Algorithms vs. Conventional Algorithms 300
9.6 Concluding Remarks 301
GLOSSARY 305
BIBLIOGRAPHY 314
INDEX 332
ABOUT THE AUTHORS 336
|
| any_adam_object | 1 |
| author | Mazumder, Pinaki Rudnick, Elisabeth M. |
| author_facet | Mazumder, Pinaki Rudnick, Elisabeth M. |
| author_role | aut aut |
| author_sort | Mazumder, Pinaki |
| author_variant | p m pm e m r em emr |
| building | Verbundindex |
| bvnumber | BV012490900 |
| classification_rvk | ST 285 ST 301 |
| classification_tum | MAT 919f ELT 272f |
| ctrlnum | (OCoLC)313311779 (DE-599)BVBBV012490900 |
| dewey-full | 621.39/5 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 621.395 |
| dewey-search | 621.39/5 621.395 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Mathematik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01939nam a2200469 c 4500</leader><controlfield tag="001">BV012490900</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20060607 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">990408s1999 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0130115665</subfield><subfield code="9">0-13-011566-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)313311779</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV012490900</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield><subfield code="a">DE-91</subfield><subfield code="a">DE-703</subfield><subfield code="a">DE-706</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.395</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 285</subfield><subfield code="0">(DE-625)143648:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 301</subfield><subfield code="0">(DE-625)143651:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">MAT 919f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Mazumder, Pinaki</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Genetic algorithms for VLSI design, layout & test automation</subfield><subfield code="b">[the complete guide to VLSI design with genetic algorithms]</subfield><subfield code="c">Pinaki Mazumder ; Elizabeth M. Rudnick</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Upper Saddle River, NJ</subfield><subfield code="b">Prentice Hall</subfield><subfield code="c">1999</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIII, 338 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Genetic algorithms</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Testing</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Genetischer Algorithmus</subfield><subfield code="0">(DE-588)4265092-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Genetischer Algorithmus</subfield><subfield code="0">(DE-588)4265092-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Rudnick, Elisabeth M.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">HBZ Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008478990&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-008478990</subfield></datafield></record></collection> |
| id | DE-604.BV012490900 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:28:31Z |
| institution | BVB |
| isbn | 0130115665 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008478990 |
| oclc_num | 313311779 |
| open_access_boolean | |
| owner | DE-29T DE-91 DE-BY-TUM DE-703 DE-706 |
| owner_facet | DE-29T DE-91 DE-BY-TUM DE-703 DE-706 |
| physical | XIII, 338 S. graph. Darst. |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | Prentice Hall |
| record_format | marc |
| spelling | Mazumder, Pinaki Verfasser aut Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] Pinaki Mazumder ; Elizabeth M. Rudnick Upper Saddle River, NJ Prentice Hall 1999 XIII, 338 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Genetic algorithms Integrated circuits Very large scale integration Design and construction Integrated circuits Very large scale integration Testing Genetischer Algorithmus (DE-588)4265092-6 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Genetischer Algorithmus (DE-588)4265092-6 s VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s DE-604 Rudnick, Elisabeth M. Verfasser aut HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008478990&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Mazumder, Pinaki Rudnick, Elisabeth M. Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] Genetic algorithms Integrated circuits Very large scale integration Design and construction Integrated circuits Very large scale integration Testing Genetischer Algorithmus (DE-588)4265092-6 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4265092-6 (DE-588)4312536-0 (DE-588)4117388-0 |
| title | Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] |
| title_auth | Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] |
| title_exact_search | Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] |
| title_full | Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] Pinaki Mazumder ; Elizabeth M. Rudnick |
| title_fullStr | Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] Pinaki Mazumder ; Elizabeth M. Rudnick |
| title_full_unstemmed | Genetic algorithms for VLSI design, layout & test automation [the complete guide to VLSI design with genetic algorithms] Pinaki Mazumder ; Elizabeth M. Rudnick |
| title_short | Genetic algorithms for VLSI design, layout & test automation |
| title_sort | genetic algorithms for vlsi design layout test automation the complete guide to vlsi design with genetic algorithms |
| title_sub | [the complete guide to VLSI design with genetic algorithms] |
| topic | Genetic algorithms Integrated circuits Very large scale integration Design and construction Integrated circuits Very large scale integration Testing Genetischer Algorithmus (DE-588)4265092-6 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Genetic algorithms Integrated circuits Very large scale integration Design and construction Integrated circuits Very large scale integration Testing Genetischer Algorithmus Entwurfsautomation VLSI |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008478990&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT mazumderpinaki geneticalgorithmsforvlsidesignlayouttestautomationthecompleteguidetovlsidesignwithgeneticalgorithms AT rudnickelisabethm geneticalgorithmsforvlsidesignlayouttestautomationthecompleteguidetovlsidesignwithgeneticalgorithms |