FPGA '99: ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999]
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Assoc. for Computing Machinery
1999
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VII, 257 S. Ill., graph. Darst. |
| ISBN: | 1581130880 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV012414790 | ||
| 003 | DE-604 | ||
| 005 | 19991220 | ||
| 007 | t | ||
| 008 | 990218s1999 ad|| |||| 10||| eng d | ||
| 020 | |a 1581130880 |9 1-58113-088-0 | ||
| 035 | |a (OCoLC)314162181 | ||
| 035 | |a (DE-599)BVBBV012414790 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-739 |a DE-20 |a DE-91G | ||
| 084 | |a SS 1999 |0 (DE-625)143436: |2 rvk | ||
| 084 | |a DAT 195f |2 stub | ||
| 111 | 2 | |a FPGA |n 7 |d 1999 |c Monterey, Calif. |j Verfasser |0 (DE-588)5331363-X |4 aut | |
| 245 | 1 | 0 | |a FPGA '99 |b ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| 264 | 1 | |a New York, NY |b Assoc. for Computing Machinery |c 1999 | |
| 300 | |a VII, 257 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Gate-Array-Bauelement |0 (DE-588)4113666-4 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1999 |z Monterey Calif. |2 gnd-content | |
| 689 | 0 | 0 | |a Gate-Array-Bauelement |0 (DE-588)4113666-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 710 | 2 | |a Association for Computing Machinery |b Special Interest Group on Design Automation |e Sonstige |0 (DE-588)10620-3 |4 oth | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008422967&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-008422967 | ||
Datensatz im Suchindex
| _version_ | 1804127050225680384 |
|---|---|
| adam_text | Table
of
Contents
Session
1.
Commercial FPGA Architectures
Chair: Jonathan
Rose, University of
Toronto
1.1
A
new high density and very low cost reprogrammable FPGA architecture, Sinan
Kaptanoglu, Greg
Bakker,
Aran
Kundu, Ivan Corneillet, Actel Corporation; Ben Ting,
BTRInc
..............................................................................................................................3
1.2
Hybrid Product Term and
LUT
Based Architectures Using Embedded Memory
Blocks, Frank
Heile,
Andrew Leaver,
Altera
Corporation
.................................................13
1.3
An Innovative, Segmented High Performance FPGA Family with Variable-Grain-
Architecture and Wide gating functions, Om Agrawal, Herman Chang, Brad Sharpe-
Geisler, Nick
Schmitz,
Bai
Nguyen, Jack Wong, Giap
Tran,
Fabiano Fontana, Bill
Harding, Vantis Corporation
.............................................................................................17
Session
2.
Mapping, Packing and Floorplanning
Chair: Margaret Marek-Sadowska, University of California, Santa Barbara
2.1
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping
Solution, Jason Cong, Chang Wu, University of California, Los Angeles, Yuzheng
Ding, Lucent Technologies
...............................................................................................29
2.2
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA
Speed and Density, Alexander Marquardt, Vaughn Betz, Jonathan Rose, University of
Toronto
.............................................................................................................................37
2.3
A Methodology for Fast FPGA Floorplanning, John
Emmert,
Dinesh
B hatia,
University of Cincinatti
.....................................................................................................47
Session
3.
FPGA Architecture Studies
Chair: Tim Southgate,
Altera
3.1
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and
Density, Vaughn Betz, Jonathan Rose, University of Toronto
...........................................59
3.2
Balancing Interconnect and Computation in
a Reconfigurable
Computing Array
(or, why you don t really want
100%
LUT
utilization), Andre DeHon, University of
California, Berkeley
..........................................................................................................69
Session
4.
Rapid Reconfiguration
Chair: Mike Butts, Synopsys
4.1
Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures, S.R.
Park, W. Burleson, University of Massachusetts
..............................................................81
4.2
Don t Care Discovery for FPGA Configuration Compression, Zhiyuan Li, Scott
Hauck, Northwestern University
.......................................................................................91
Session 5.
Computational
Applications
Chair: Brad Hutchings, Brigham Young University
5.1
A FPGA-Based Hardware Implementation of Generalized Profile Search Using
Online Arithmetic, Emeka Mosanya,
Eduardo
Sanchez, Swiss Federal Institute of
Technology
.....................................................................................................................101
5.2
Procedural Texture Mapping on FPGAs, Andy G. Ye, David M. Lewis, University
of Toronto
......................................................................................................................112
Panel: FPGAs in the Era of Systems-on-a-Chip
Moderator: Scott Hauck, Northwestern University
..........................................................121
Session
6.
FPGAs for Custom Computing
Chair: Carl Ebeling, University of Washington
6.1
HSRA: High-Speed, Hierarchical Synchronous
Reconfigurable
Array, William
Tsu, Kip
Масу,
Atui
Joshi, Randy Huang, Norman Walker, Tony Tung, Omid
Rowhani,
Varghese
George, John Wawrzynek, Andre DeHon, University of
California, Berkeley
........................................................................................................125
6.2
A Reconfigurable
Arithmetic Array for Multimedia Applications, Alan Marshall,
Hewlett Packard;
Jean Vuillemin, Ecole Normale
Superieure;
Tony Stansfield, Igor
Kostarnov, Hewlett Packard;
Brad
Hutchings, Brigham
Young University.....................
135
6.3 Memory
Interfacing and Instruction Specification for
Reconfigurable
Processors,
Jeffrey A Jacob, Paul Chow, University of Toronto
.......................................................145
Session
7.
Placement and Routing
Chair:
Martine
Schlag,
University of California, Santa Cruz
7.1
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs, Yaska
Sankar, Jonathan Rose, University of Toronto
................................................................
7.2
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via
Search-Based Boolean SAT, Gi-Joon
Nam, Karem
A. Sakallah, University of
Michigan; Rob A.
Rutenbar,
Carnegie Mellon University
...............................................
7.3
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems,
Abdel
Ejnioui; University of South Florida;
N.
Ranganathan, University of Texas
..........176
Session
8.
DPGAs and Pipeline Configurable FPGAs
Chair: David Lewis, University of Toronto
8.1
Circuit Partitioning for Dynamically
Reconfigurable
FPGAs, Huiqun Liu, D.F.
Wong, University of Texas
.............................................................................................187
8.2
Fast Compilation for Pipelined
Reconfigurable
Fabrics, Mihai Budiu, Seth
Copen
Goldstein, Carnegie Mellon University
...........................................................................195
8.3
Configuration Caching Vs Data Caching for Striped FPGAs, Deepali Deshpande,
Arun
К
Somam,
Akhilesh Tyagi, Iowa State University
.................................................206
Session 9. Applications
Chair:
Ray Andraka,
And raka
Consulting Group
9.1
String Matching on Multicontext FPGAs using Self-Reconfiguration, Reetinder
P.S.
Sidhu,
Alessandro Mei,
Viktor
К.
Prasanna, University of Southern California
......217
9.2
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for
FPGAs, P. Kollig, B.M. Al-Hashimi, Staffordshire University
.......................................227
9.3
Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded
System,
Karlheinz
Weiss,
Thorsten Steckstor,
Gernot Koch, Wolfgang
Rosenstiel,
University of Tubingen
...................................................................................................235
Poster Paper Abstracts
................................................................................................243
Author Index
.....................................................................................................................257
|
| any_adam_object | 1 |
| author_corporate | FPGA Monterey, Calif |
| author_corporate_role | aut |
| author_facet | FPGA Monterey, Calif |
| author_sort | FPGA Monterey, Calif |
| building | Verbundindex |
| bvnumber | BV012414790 |
| classification_rvk | SS 1999 |
| classification_tum | DAT 195f |
| ctrlnum | (OCoLC)314162181 (DE-599)BVBBV012414790 |
| discipline | Informatik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01563nam a2200349 c 4500</leader><controlfield tag="001">BV012414790</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19991220 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">990218s1999 ad|| |||| 10||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1581130880</subfield><subfield code="9">1-58113-088-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)314162181</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV012414790</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-739</subfield><subfield code="a">DE-20</subfield><subfield code="a">DE-91G</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">SS 1999</subfield><subfield code="0">(DE-625)143436:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 195f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">FPGA</subfield><subfield code="n">7</subfield><subfield code="d">1999</subfield><subfield code="c">Monterey, Calif.</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5331363-X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">FPGA '99</subfield><subfield code="b">ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999]</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York, NY</subfield><subfield code="b">Assoc. for Computing Machinery</subfield><subfield code="c">1999</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">VII, 257 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Gate-Array-Bauelement</subfield><subfield code="0">(DE-588)4113666-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1999</subfield><subfield code="z">Monterey Calif.</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Gate-Array-Bauelement</subfield><subfield code="0">(DE-588)4113666-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="710" ind1="2" ind2=" "><subfield code="a">Association for Computing Machinery</subfield><subfield code="b">Special Interest Group on Design Automation</subfield><subfield code="e">Sonstige</subfield><subfield code="0">(DE-588)10620-3</subfield><subfield code="4">oth</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008422967&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-008422967</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 1999 Monterey Calif. gnd-content |
| genre_facet | Konferenzschrift 1999 Monterey Calif. |
| id | DE-604.BV012414790 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:27:11Z |
| institution | BVB |
| institution_GND | (DE-588)5331363-X (DE-588)10620-3 |
| isbn | 1581130880 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008422967 |
| oclc_num | 314162181 |
| open_access_boolean | |
| owner | DE-739 DE-20 DE-91G DE-BY-TUM |
| owner_facet | DE-739 DE-20 DE-91G DE-BY-TUM |
| physical | VII, 257 S. Ill., graph. Darst. |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | Assoc. for Computing Machinery |
| record_format | marc |
| spelling | FPGA 7 1999 Monterey, Calif. Verfasser (DE-588)5331363-X aut FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] New York, NY Assoc. for Computing Machinery 1999 VII, 257 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Gate-Array-Bauelement (DE-588)4113666-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1999 Monterey Calif. gnd-content Gate-Array-Bauelement (DE-588)4113666-4 s DE-604 Association for Computing Machinery Special Interest Group on Design Automation Sonstige (DE-588)10620-3 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008422967&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] Gate-Array-Bauelement (DE-588)4113666-4 gnd |
| subject_GND | (DE-588)4113666-4 (DE-588)1071861417 |
| title | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| title_auth | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| title_exact_search | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| title_full | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| title_fullStr | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| title_full_unstemmed | FPGA '99 ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| title_short | FPGA '99 |
| title_sort | fpga 99 acm sigda international symposium on field programmable gate arrays monterey california february 21 23 1999 |
| title_sub | ACM SIGDA International Symposium on Field Programmable Gate Arrays ; [Monterey, California, February 21 - 23, 1999] |
| topic | Gate-Array-Bauelement (DE-588)4113666-4 gnd |
| topic_facet | Gate-Array-Bauelement Konferenzschrift 1999 Monterey Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008422967&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT fpgamontereycalif fpga99acmsigdainternationalsymposiumonfieldprogrammablegatearraysmontereycaliforniafebruary21231999 AT associationforcomputingmachineryspecialinterestgroupondesignautomation fpga99acmsigdainternationalsymposiumonfieldprogrammablegatearraysmontereycaliforniafebruary21231999 |