Proceedings:
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Assoc. for Computing Machinery
1998
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XI, 318 S. Ill., graph. Darst. |
| ISBN: | 1581130597 0780350685 |
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| 300 | |a XI, 318 S. |b Ill., graph. Darst. | ||
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Datensatz im Suchindex
| _version_ | 1804126916683235328 |
|---|---|
| adam_text | TABLE
OF
CONTENTS
Keynote
Session MO
Chair: Anantha
Chandrakasan
Session M0.1
High
Performance
DSPs - What s Hot and What s Not?
Bryan Ackland, Chris
Nicol
........................................................................
Session M0.2
Low Power and Low Voltage CMOS Digital Circuits Techniques
Christer Svensson,
Atila
Alvandpour
.......................................................................................7
Session Ml
RF Building Blocks
Session Chair: Lou Williams
Associate Chair: T. R. Viswanathan
Ml.l CMOS Front End Components for
Micropower RF
Wireless Systems
Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser
............................11
M1.2 A 1.4-GHz 3-mW CMOS LC Low Phase Noise VCO Using Tapped Bond Wire
Inductance
Tamara
I. Ahrens, Thomas H. Lee
..........................................................................................16
M1.3 A 3.8-mW 2.5-GHz Dual-Modulus Prescaler in a
0.8
μΐη
Silicon Bipolar Production
Technology
Herbert
Knapp,
Wilhelm Wilhelm, Mira
Rest, Hans-Peter Trost...........................................20
Session
М2
RT-Level Power
Modeling and Analysis
Session Chair: Jose
Monteiro
Associate Chair:
Luca
Benini
M2.1 Towards the Capability of Providing Power-Area-Delay Trade-off at the Register
Transfer Level
Chun-hong Chen, Chi-ying Tsui
.............................................................................................24
M2.2 Stream Synthesis for Efficient Power Simulation Based on Spectral Transforms
Alberto
Macii,
Enrico
Macii,
Massimo Poncino, Riccardo
Scarsi
........................................30
M2.3 Theoretical Bounds for Switching Activity Analysis in Finite-State Machines
Diana Marculescu,
Radu
Marculescu, Massoud Pedram
......................................................36
Session M3
Enabling Device Technology for Low-Power Applications
Session Chair: Bill Kaiser
Associate Chair: Jim Burr
M3.1 Low Power Salient Integration Mode Image Sensor with a Low Voltage Mixed-Signal
Readout Architecture
Eric Y. Chou,
A. J.
Budrys,
Kit
M.
Cham
...............................................................................42
M3.2 A Delay Distribution Squeezing Scheme with Speed-Adaptive Threshold-Voltage
CMOS (SA-Vt CMOS) for Low Voltage LSIs
Masayuki
Miyazaki,
Hiroyuki Mizuno, Koichiro Ishibashi
....................................................48
M3.3
3D
CMOS SOI for High Performance Computing
S. J. Abou-Samra, P. A. Aisa, A. Guyot, B.
Courtois
..............................................................54
M3.4
A High Speed and Low Power SOI Inverter using Active Body-Bias
Joonho Gil, Minkyu
Je, Jongho
Lee, Hyungcheol Shin
.........................................................59
Sessions M4
Low-Power Architectural Techniques for General Purpose Systems
Session Chair: Vivek Tiwari
Associate Chair: Chris
Nicol
M4.1 Power and Performance Tradeoffs using Various Caching Strategies
R. Ms Bahar, Gianluca
Albera, Srilatha Manne
...................................................................64
M4.2 Architectural and Compiler Support for Energy Reduction in the Memory
Hierarchy of High Performance Microprocessors
Nikolaos Bellas, Ibrahim Hajj,
Constantine Polychronopoulos,
George Stamoulis
.............70
M4.3 The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms
Trevor
Pering,
Tom
Burd,
Robert Brodersen
.........................................................................76
M4.4 Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs
Таки
Ohsawa,
Koji
Kai, Kazuaki
Murakami
..........................................................................82
Session PI
Circuits and Technology
Session Chair: Sayfe Kiaei
Pl.l Integrated DC/DC Converter with Digital Controller
Ferdinand Sluijs,
Kees Hart, Wouter
Groeneveld,
Stephan Haag.........................................88
¥12
CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry
Rafaela.
Betancourt-Zamora, Thomas H. Lee
......................................................................91
P13 The Impact of Data Characteristics and Hardware Topology on Hardware
Selection for Low Power DSP
Gareth
Keane,
Jonathan
Spanier,
Roger Woods
....................................................................94
P1.4 Low Threshold CMOS Circuits with Low Standby Current
MirceaRStan
........................................................................................................................97
P1.5 Minimum Supply Voltage for Bulk Si CMOS GSI
AzeezJ. Bhavnagarwala,
Blanca
Austin, James D. Meindl
................................................100
P1.6
0.5
V CMOS Logic Delivering
200
Million
8x8
Bit Multiplications/s at Less
Than
100
f J
Based on a
50
nm
Т
-Gate SOI Technology
Volter
Dudek,
Reinhard Grube, Bernd Höfflinger, Michael Schau.....................................103
P1.8
Decreasing Low-Voltage Manufacturing-Induced Delay Variations with
Adaptive Mixed-Voltage-Swing Circuits
L
Richard Carley, Abhay Aggarwal, Ram K. Krishnamurthy
............................................106
P1.9 Power-Delay Tradeoffs for Radix-4 and Radix-8 Dividers
Alberto Nannarelli,
Tomas Lang..........................................................................................109
Session P2
Systems and CAD
Session Chair.
Ingrid
Verbauwhede
P2.1 Automatic Characterization and Modeling of Power Consumption in Static
RAM s
Mauro Chinosi,
Roberto Zafalon, Carlo
Guardiani
.............................................................112
P2.2 Improving Sampling Efficiency for System Level Power Estimation
Chih-Shun Ding, Cheng
-Та
Hsieh, Massoud Pedram
..........................................................115
P23 Power Invariant Vector Compaction Based on Bit Clustering and Temporal
Partitioning
Nicola
Dragone,
Roberto Zafalon, Carlo
Guardiani,
Cristina Silvano
...............................
П8
vi
P2.4
An Empirical Comparison of Algorithmic, Instruction, and Architectural
Power Prediction Models for High Performance Embedded DSP Processors
Catherine H. Gebotys, Robert J. Gebotys
............................................................................121
P2.5 Power Calculation and Modeling in Deep
Submicron
Jay Abraham
.........................................................................................................................124
P2.6 Partial Bus-Invert Coding for Power Optimization of System Level Bus
Youngsoo Shin, Sook-Ik Chae, Kiyoung Choi
......................................................................127
P2.7 The Petrol Approach to High-Level Power Estimation
Rafael
Peset Llopis,
Kees Goossens
.....................................................................................130
P2.8 Power Consumption of Parallel Spread Spectrum Correlator Architectures
Won Namgoong, Teresa
Meng..............................................................................................133
P2.9 A Low Power Video Processor
Uzi Zangi,
Ran Ginosar.
.......................................................................................................136
P2.10 Power Dissipated by CMOS Gates Driving Lossless Transmission Lines
Yehea I. Ismail, Eby G. Friedman, Jose L. Neves
................................................................139
Panel
Past and Future Blockbusters in Low-Power Design
Moderator: Jan M. Rabaey
Bryan Ackland, Bob Brodersen,
Christer Svenson,
Bruce Wooley
......................................142
Invited Talks Session TO
Session Chair:
Fand N.
Najm
TO.l Emerging Power Management Tools for Processor Design
D.
Т. ВкшищА.
Dharchoudhury,
R
Panda,
S. Sirichotiyakul, C
Oh, T. Edwards
............143
T0.2 Recent Developments in High Integration Multi-Standard CMOS Transceivers
for Personal Communication Systems
Jacque
С
Rudell, Jia-Jiunn
Ou,
Sekhar Narayanaswami, George
Chien,
Jeffrey A.
Weldon,
Li Lin, King-Chun Tsai,
Luns
Tee, Kelvin Khoo,
Danelle
Au,
Troy Robinson,
Danilo
Gema,
Masanori Otsuka, Paul Gray
.............................................149
Session Tl
Low-Power Logic Circuits
Session Chair: Brock Barton
Associate Chair: Rick Carley
Tl.l Low-Energy Embedded FPGA Structures
Eric Kusse, Jan M.
Rabaey
..................................................................................................155
T1.2 Low Swing Interconnect Interface Circuits
Hui
Zhang, Jan Rabaey
........................................................................................................161
T13 True Single-Phase Energy-Recovering Logic for Low-Power, High-Speed VLSI
Suhwan Kim, Marios C. Papaefihymiou
..............................................................................167
Session T2
System Level Power Issues
Session Chair:
Renu
Mehra
Associate Chair:
Maurizio Damiani
T2.1 System-Level Power Estimation and Optimization
Luca
Benini,
Robin Hodgson, Polly
Siegel..........................................................................173
Ί22
Memory Modeling for System Synthesis
Sari
L
Coumeri, Donald E. Thomas
....................................................................................179
T2.3
Monitoring System
Activity for OS-Directed Dynamic Power Management
Luca
Benini,
Alessandro Bugliolo, Stefano Cavallucci, Bruno Ricco
.................................185
Session T3
Variable Voltage and Analog Techniques
Session Chair: Christian
Enz
Associate Chair:
Venu
Gopinathan
T3.1
A Reconfigurable
Dual Output Low Power Digital PWM Power Converter
Abram
Dancy, Anantha
Chandrakasan................................................................................191
T3.2 Voltage Scheduling Problem for Dynamically Variable Voltage Processors
Tohru Ishihara, Hiroto Yasuura
............................................................................................197
T33 On the Optimum Design of Regulated Cascode Operational Transconductance
Amplifiers
Thomas Burger, Qiuting Huang
...........................................................................................203
Sessions T4
Logic Synthesis for Low Power
Session Chair: George Stamoulis
Associate Chair:
Sarma
Vrudhula
T4.1 Low Power Logic Synthesis under a General Delay Model
Unni
Narayanan, PeichenPan, C. L. Liu
............................................................................209
T4.2 Local Transformation Techniques for Multi-Level Logic Circuits Utilizing
Circuit Symmetries for Power Reduction
Ki-Seok Chung,
C. L
Uu
.....................................................................................................215
T4J A Power Optimization Method Considering Glitch Reduction by Gate Sizing
Masanori Hashimoto, Hidetoshi Onodera, Keikichi
Tamaru
..............................................221
Session T5
Circuit-Level Power Analysis and Estimation
Session Chair: Suresh Rajgopal
Associate Chair: Chi-Ying Tsui
T5.1 A Unified Approach in the Analysis of Latches and Flip-Flops for Low-Power
Systems
Vladimir Stojanovic, Vojin Oklobdzija,
Raminder
Bajwa
....................................................227
T5
2
Estimation of Maximum Power Supply Noise for Deep Sub-Micron Designs
Yi-Min Jiang, Kwang-Tmg Cheng, An-Chang Deng
............................................................233
Ί53
Estimation of Standby Leakage Power in CMOS Circuits Considering
Accurate Modeling of Transistor Stacks
Zhanping Chen, Mark Johnson, Liqiong Wei, KaushikRoy
................................................239
Ύ5Α
Separation and Extraction of Short-Circuit Power Consumption in Digital
CMOS VLSI Circuits
Atila
Alvandpour, Per Larsson-Edefors,
Christer Svensson................................................
245
Session T6
Low-Power Design for Application Specific Processors
Session Chair Naresh Shanbhag
Associate Chair:
Mary Jane Irwin
T6.1 Decorreteting (DECOR) Transformations for Low-Power Adaptive Filters
Sumant Ramprasad, Naresh
R
Shanbhag, Ibrahim
N.
Hajj
................................................250
Ύ62
The Logarithmic Number System for Strength Reduction in Adaptive Filtering
John R.
Sacha,
Mary Jane Irwin........................... ......256
vin
T6.3
Low-Power Architecture of the Soft-Output Viterbi Algorithm
David Garrett, Mircea Stan
..................................................................................................262
T6.4 Low Power Methodology and Design Techniques for Processor Design
J. Patrick Brennan,
Alvar
Dean, Stephen Kenyon, Sebastian Ventrone
..............................268
Invited Talks Session WO
Session Chair: Chuck Traylor
W0.1 Power Distribution in High-Performance Design
Michael
Benoit,
Sandy Taylor, David Overhauser,
Steffen
Rochel......................................
274
W0.2 Low-Power Miniaturized Information Display Systems
Michael Bolotski, Philip Alvelda
..........................................................................................279
Session Wl
Low-Power Memory
Session Chair: Bill Athas
Associate Chair: Dan Dobberpuhl
Wl.l Low-Power Embedded SRAM Macros with Current-Mode Read/Write Operations
Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng.
....................................................................282
W1.2 A Three-Port Adiabatic Register File Suitable for Embedded Applications
Stephen Avery, Marwan Jabri
...............................................................................................288
W1.3 A Low Power SRAM using
Auto-Backgate-Controlled MT-CMOS
Koji
NU,
Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima,
Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori
Hamáno
...............293
Session W2
High-Level Power Analysis and Optimization
Session Chair: Anand Raghunathan
Associate Chair: Joerg
Henkel
W2.1 Fast High-Level Power Estimation for Control-Flow Intensive Designs
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
.................................................299
W2.2 The Energy Complexity of Register Files
Victor Zyuban, P.
Kogge.......................................................................................................305
W2.3 Power Exploration for Dynamic Data Types Through Virtual Memory
Management Refinement
Julio L.
da Silva
Jr.,
Francky
Catthoor,
Diederik Verkest,
Hugo
De Man...........................311
|
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| genre | (DE-588)1071861417 Konferenzschrift 1998 Monterey Calif. gnd-content |
| genre_facet | Konferenzschrift 1998 Monterey Calif. |
| id | DE-604.BV012291224 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:25:03Z |
| institution | BVB |
| institution_GND | (DE-588)5306220-6 |
| isbn | 1581130597 0780350685 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008334047 |
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| physical | XI, 318 S. Ill., graph. Darst. |
| publishDate | 1998 |
| publishDateSearch | 1998 |
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| publisher | Assoc. for Computing Machinery |
| record_format | marc |
| spelling | International Symposium on Low Power Electronics and Design 1998 Monterey, Calif. Verfasser (DE-588)5306220-6 aut Proceedings 1998 International Symposium on Low Power Electronics and Design New York, NY Assoc. for Computing Machinery 1998 XI, 318 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Niederspannung (DE-588)4171864-1 gnd rswk-swf Elektronik (DE-588)4014346-6 gnd rswk-swf Nachrichtentechnik (DE-588)4041066-3 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1998 Monterey Calif. gnd-content Nachrichtentechnik (DE-588)4041066-3 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Elektronik (DE-588)4014346-6 s Niederspannung (DE-588)4171864-1 s 1\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008334047&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings Schaltungsentwurf (DE-588)4179389-4 gnd Niederspannung (DE-588)4171864-1 gnd Elektronik (DE-588)4014346-6 gnd Nachrichtentechnik (DE-588)4041066-3 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4171864-1 (DE-588)4014346-6 (DE-588)4041066-3 (DE-588)1071861417 |
| title | Proceedings |
| title_auth | Proceedings |
| title_exact_search | Proceedings |
| title_full | Proceedings 1998 International Symposium on Low Power Electronics and Design |
| title_fullStr | Proceedings 1998 International Symposium on Low Power Electronics and Design |
| title_full_unstemmed | Proceedings 1998 International Symposium on Low Power Electronics and Design |
| title_short | Proceedings |
| title_sort | proceedings |
| topic | Schaltungsentwurf (DE-588)4179389-4 gnd Niederspannung (DE-588)4171864-1 gnd Elektronik (DE-588)4014346-6 gnd Nachrichtentechnik (DE-588)4041066-3 gnd |
| topic_facet | Schaltungsentwurf Niederspannung Elektronik Nachrichtentechnik Konferenzschrift 1998 Monterey Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008334047&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationalsymposiumonlowpowerelectronicsanddesignmontereycalif proceedings |