Digital systems testing and testable design:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York
IEEE Press
c 1990
|
| Ausgabe: | Rev. print. |
| Schriftenreihe: | Electrical engineering, circuits and systems, computers
|
| Schlagworte: | |
| Beschreibung: | XVII, 652 S. graph. Darst. |
| ISBN: | 0780310624 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1820889856542244864 |
|---|---|
| adam_text | |
| any_adam_object | |
| author | Abramovici, Miron Breuer, Melvin A. Friedman, Arthur D. |
| author_facet | Abramovici, Miron Breuer, Melvin A. Friedman, Arthur D. |
| author_role | aut aut aut |
| author_sort | Abramovici, Miron |
| author_variant | m a ma m a b ma mab a d f ad adf |
| building | Verbundindex |
| bvnumber | BV012266736 |
| callnumber-first | T - Technology |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
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| classification_tum | ELT 468f |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Rev. print. |
| format | Book |
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| id | DE-604.BV012266736 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T19:04:48Z |
| institution | BVB |
| isbn | 0780310624 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008313944 |
| oclc_num | 31415783 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-859 DE-634 |
| owner_facet | DE-91 DE-BY-TUM DE-859 DE-634 |
| physical | XVII, 652 S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | IEEE Press |
| record_format | marc |
| series2 | Electrical engineering, circuits and systems, computers |
| spelling | Abramovici, Miron Verfasser aut Digital systems testing and testable design Miron Abramovici ; Melvin A. Breuer ; Arthur D. Friedman Rev. print. New York IEEE Press c 1990 XVII, 652 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Electrical engineering, circuits and systems, computers Circuitos integrados larpcal Circuits intégrés numériques ram modélisation erreur inriac modélisation inriac simulation erreur inriac simulation logique inriac système digital inriac test fonctionnel inriac testabilité inriac Digital integrated circuits Design and construction Digital integrated circuits Testing Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Prüfung (DE-588)4047609-1 gnd rswk-swf Computersimulation (DE-588)4148259-1 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 gnd rswk-swf Testkonstruktion (DE-588)4124306-7 gnd rswk-swf Fehlererkennung (DE-588)4133764-5 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Digitales System (DE-588)4012300-5 gnd rswk-swf Testbarkeit (DE-588)4271826-0 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf Digitales System (DE-588)4012300-5 s Prüftechnik (DE-588)4047610-8 s DE-604 Testbarkeit (DE-588)4271826-0 s Schaltungsentwurf (DE-588)4179389-4 s 1\p DE-604 VLSI (DE-588)4117388-0 s 2\p DE-604 Prüfung (DE-588)4047609-1 s 3\p DE-604 4\p DE-604 Fehlererkennung (DE-588)4133764-5 s 5\p DE-604 Digitaltechnik (DE-588)4012303-0 s 6\p DE-604 Computersimulation (DE-588)4148259-1 s 7\p DE-604 Testkonstruktion (DE-588)4124306-7 s Breuer, Melvin A. Verfasser aut Friedman, Arthur D. Verfasser aut 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 6\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 7\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Abramovici, Miron Breuer, Melvin A. Friedman, Arthur D. Digital systems testing and testable design Circuitos integrados larpcal Circuits intégrés numériques ram modélisation erreur inriac modélisation inriac simulation erreur inriac simulation logique inriac système digital inriac test fonctionnel inriac testabilité inriac Digital integrated circuits Design and construction Digital integrated circuits Testing Schaltungsentwurf (DE-588)4179389-4 gnd Prüfung (DE-588)4047609-1 gnd Computersimulation (DE-588)4148259-1 gnd Digitaltechnik (DE-588)4012303-0 gnd Testkonstruktion (DE-588)4124306-7 gnd Fehlererkennung (DE-588)4133764-5 gnd VLSI (DE-588)4117388-0 gnd Digitales System (DE-588)4012300-5 gnd Testbarkeit (DE-588)4271826-0 gnd Prüftechnik (DE-588)4047610-8 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4047609-1 (DE-588)4148259-1 (DE-588)4012303-0 (DE-588)4124306-7 (DE-588)4133764-5 (DE-588)4117388-0 (DE-588)4012300-5 (DE-588)4271826-0 (DE-588)4047610-8 |
| title | Digital systems testing and testable design |
| title_auth | Digital systems testing and testable design |
| title_exact_search | Digital systems testing and testable design |
| title_full | Digital systems testing and testable design Miron Abramovici ; Melvin A. Breuer ; Arthur D. Friedman |
| title_fullStr | Digital systems testing and testable design Miron Abramovici ; Melvin A. Breuer ; Arthur D. Friedman |
| title_full_unstemmed | Digital systems testing and testable design Miron Abramovici ; Melvin A. Breuer ; Arthur D. Friedman |
| title_short | Digital systems testing and testable design |
| title_sort | digital systems testing and testable design |
| topic | Circuitos integrados larpcal Circuits intégrés numériques ram modélisation erreur inriac modélisation inriac simulation erreur inriac simulation logique inriac système digital inriac test fonctionnel inriac testabilité inriac Digital integrated circuits Design and construction Digital integrated circuits Testing Schaltungsentwurf (DE-588)4179389-4 gnd Prüfung (DE-588)4047609-1 gnd Computersimulation (DE-588)4148259-1 gnd Digitaltechnik (DE-588)4012303-0 gnd Testkonstruktion (DE-588)4124306-7 gnd Fehlererkennung (DE-588)4133764-5 gnd VLSI (DE-588)4117388-0 gnd Digitales System (DE-588)4012300-5 gnd Testbarkeit (DE-588)4271826-0 gnd Prüftechnik (DE-588)4047610-8 gnd |
| topic_facet | Circuitos integrados Circuits intégrés numériques modélisation erreur modélisation simulation erreur simulation logique système digital test fonctionnel testabilité Digital integrated circuits Design and construction Digital integrated circuits Testing Schaltungsentwurf Prüfung Computersimulation Digitaltechnik Testkonstruktion Fehlererkennung VLSI Digitales System Testbarkeit Prüftechnik |
| work_keys_str_mv | AT abramovicimiron digitalsystemstestingandtestabledesign AT breuermelvina digitalsystemstestingandtestabledesign AT friedmanarthurd digitalsystemstestingandtestabledesign |