ACM SIGDA International Symposium on Field Programmable Gate Arrays: FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York
ACM
1998
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VII, 262 S. graph. Darst. |
| ISBN: | 0897919785 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1804126632215052288 |
|---|---|
| adam_text | Table
of Contents
Session-
1:
New FPGA Architectures
Session chair: Jonathan Rose, University of Toronto.
1.1
A Novel Predictable Segmented FPGA Routing Architecture,
Emil Ochotta,
Patrick Crotty, Chuck Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard
Li, Joe Linoff, Luan Ngo,
Ну
Nguyen, Kerry Pierce, Doug
Wieland,
Jennifer
Zhuang, Scott Nance,
Xilinx Inc
............................................................................... 3
1.2
More wires and fewer LUTs: A design methodology for FPGAs, Atsushi Taka-
hara, Toshiaki
Miyazaki, Takahiro
Murooka, Masaru Katayama, Takaki Ichimori,
Kazuhiro Hayashi, Akihiro Tsutsui, Ken-nosuke Fukami, NTT Optical Network
System Laboratories
.................................................................................................. 12
1.3
Optimizations for a Highly Cost Efficient Programmable Logic Architecture,
Kerry Veenstra, Bruce Pedersen, Jay
Schleicher, Chiakang
Sung,
Altera Corp
........ 20
Session-2: Technology Mapping for FPGAs
Session chair:
Fabrizio
Lombardi,
Texas A&M University.
2.1
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application
to Architecture Evaluation, Jason Cong, Yean-Yow Hwang, UCLA
..................... 27
2.2
A New Retiming-based Technology Mapping Algorithm for LUT-based
FPGAs, Paichen Pan,
Clarkson
University;
С. С
Lin, Mentor Graphics
................. 35
Session-3: Multi-FPGA Systems
&
Other Reprogrammable
Architectures
Session chair: Steve Trimberger, Xilinx Inc.
3.1
A Hybrid Complete Graph Partial Crossbar Routing Architecture for
Multi
FPGA Systems, Mohammed A. Khalid, Jonathan Rose, University of Toronto
...... 45
3.2
Managing Pipeline
Reconfigurable
FPGAs, Srihari Cadambi, Jeffrey Weener,
Seth Goldstein, Herman Schmit, Donald Thomas, Carnegie Mellon University
....... 55
3.3
Configuration Prefetch for Single Context
Reconfigurable
Coprocessors, Scott
Hauck, Northwestern University
................................................................................ 65
Session-4: Partitioning and Floor Planning for FPGAs
Session chair: Jason Cong, UCLA.
4.1
Circuit Partitioning with Complex Resource Constraints in FPGAs, Huiqun
Liu, D. F. Wong, University of Texas at Austin;
Kai
Zhu, Actel Corporation
........... 77
4.2
Timing Driven Floor Planning on Programmable Hierarchical Targets,
S.A.
Senouci, A. Amoura, H. Krupnova, G. Saucier,
Institut
National
Polytechnique de
Gronoble
.................................................................................................................... 85
Session-5: Fault Detection and Fault Tolerance for FPGAs
Session chair: Herman Schmit, Carnegie-Mellon University.
5.1
Bridging Fault Detection in FPGA Interconnects using IDDq, L. Zhao, D. M.
H. Walker, F.
Lombardi,
Texas A&M University
...................................................... 95
5.2
Efficiently Supporting Fault Tolerance in FPGAs, John
Lach,
William H. Man-
gione-Smith, Miodrag Potkonjak, UCLA
.................................................................. 105
Evening Panel Discussion: Impossible demands and constraints from hell; how to
tell what makes a good FPGA. Organizer: Jonathan Rose, University of Toronto,
Moderator: Sinan Kaptanoglu, Actel Corporation
...................................................
Session-6: Fast CAD Tools for FPGAs
Session chair: Carl Ebeling, University of Washington.
6.1
Fast Module Mapping and Placement for Datapaths in FPGAs, Timothy J.
Callahan,
Phillip Chong,
André DeHon,
John Wawrzynek, University of California
at Berkeley
................................................................................................................. 123
6.2
Fast Integrated Tools for Circuit Design with FPGAs,
Stephan
W.
Gehring,
Ste¬
fan H.-M.
Ludwig, Institute
for
Computer Systems,
Swiss Federal
Institute
of
Technology................................................................................................................ 133
6.3
A
Fast Routability-Driven
Router for
FPGAs, Jordan S. Swartz,
Vaughn Betz,
Jonathan
Rose, University of
Toronto....................................................................... 140
Session-7:
Time Multiplexed
FPGAs
Session
chair:
Sinan Kaptanoglu, Actel Corporation.
7.1
Scheduling
Designs
into a Time-Multiplexed
FPGA, Steve Trimberger, Xilinx. 153
7.2
Partitioning Sequential Circuits on Dynamically
Reconfigurable
FPGAs, Dou¬
glas Chang,
Małgorzata Marek-Sadowska,
University of California at Santa Bar-
161
bara
....................
Session-8: Technology Mapping for FPGAs with Embedded Memory
Session chair: Scott Hauck, Northwestern University.
8.1
SMAP: Heterogeneous Technology Mapping for FPGAs with Embedded
Memory Arrays, Steven J. E. Wilton, University of British Columbia
....................
l71
8.2
Technology Mapping for FPGAs with Embedded Memory Blocks, Jason Cong,
Songjie Xu, UCLA
...................... ............ 179
Session-9:
Novel FPGA Applications
Session chair: Michael Butts, Quickturn Systems.
9.1
A Survey of CORDIC algorithms for FPGA based computers, Ray Andraka,
the Andraka Consulting Group
.................................................................................. 191
9.2
FPGA-Based Sonar Processing, Paul Graham, Brent Nelson, Brigham Young
University
.................................................................................................................. 201
9.3
Evolving Computer Programs using Rapidly
Reconfigurable
FPGAs and
Genetic Programming, John
R. Koza,
Forrest H. Bennett III, Stanford University;
Jeffrey L. Hutchings, Stephen L. Bade, Convergent Design,
L.L.C.
;
Martin A.
Keane,
Martin
Keane
Inc.; David Andre, University of California at Berkeley
......... 209
Session-lO: Programmable Architectures with Special Features
Session chair: Dwight Hill, Synopsys Inc.
10.1
High Performance Carry Chains for FPGAs, Scott Hauck, Matthew Hosier,
Thomas Fry, Northwestern University
....................................................................... 223
10.2
A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering,
James R. Anderson, Siddharth Sheth, Intel Corp.; Kaushik Roy, Purdue University.
234
10.3
An LPGA with Foldable PLA-Style Logic Blocks, Jason H. Anderson, Stephen
D. Brown, University of Toronto
............................................................................... 244
Appendix
Poster Paper Abstracts (listed alphabetically by title)
............................................ 255
|
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| author_corporate | FPGA Monterey, Calif |
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| language | English |
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| physical | VII, 262 S. graph. Darst. |
| publishDate | 1998 |
| publishDateSearch | 1998 |
| publishDateSort | 1998 |
| publisher | ACM |
| record_format | marc |
| spelling | FPGA 6 1998 Monterey, Calif. Verfasser (DE-588)5280841-5 aut ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 FPGA '98 New York ACM 1998 VII, 262 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008145543&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| subject_GND | (DE-588)1071861417 |
| title | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| title_alt | FPGA '98 |
| title_auth | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| title_exact_search | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| title_full | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| title_fullStr | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| title_full_unstemmed | ACM SIGDA International Symposium on Field Programmable Gate Arrays FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| title_short | ACM SIGDA International Symposium on Field Programmable Gate Arrays |
| title_sort | acm sigda international symposium on field programmable gate arrays fpga 98 doubletree hotel monterey california february 22 24 1998 |
| title_sub | FPGA '98 ; [Doubletree Hotel, Monterey, California, February 22 - 24, 1998 |
| topic_facet | Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008145543&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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