Proceedings: ISPD-98 ; Monterey, CA, April 6-8, 1998
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York
ACM
1998
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | IX, 220 S. graph. Darst. |
| ISBN: | 158113021X |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV012037475 | ||
| 003 | DE-604 | ||
| 005 | 19981102 | ||
| 007 | t | ||
| 008 | 980702s1998 d||| |||| 10||| eng d | ||
| 020 | |a 158113021X |9 1-58113-021-X | ||
| 035 | |a (OCoLC)39104726 | ||
| 035 | |a (DE-599)BVBBV012037475 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 050 | 0 | |a TK7874.75 | |
| 084 | |a DAT 190f |2 stub | ||
| 111 | 2 | |a International Symposium on Physical Design |n 2 |d 1998 |c Monterey, Calif. |j Verfasser |0 (DE-588)5294784-1 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b ISPD-98 ; Monterey, CA, April 6-8, 1998 |c 1998 International Symposium on Physical Design |
| 246 | 1 | 3 | |a ISPD-98 |
| 264 | 1 | |a New York |b ACM |c 1998 | |
| 300 | |a IX, 220 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Integrated circuits |x Very large scale integration |v Congresses | |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |2 gnd-content | |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008145491&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-008145491 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804126632156332032 |
|---|---|
| adam_text | Table
of
Contents
Foreword
.......................................................................iv
Symposium
Organization
..........................................................
v
Table
of Contents
................................................................
vi
Keynote Address
•
Design of a 1GHZ Processor
David LaPotin
Session
1:
Floorplanning and Placement
Moderators: C.-K. Cheng (UCSD)
J. Jess (Eindhoven)
•
On Wirelength Estimations for Row-Based Placement
.......................................4
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L· Markov and A. Zelikovsky (UCLA)
•
Performance-Driven Soft-Macro Clustering and Placement by Preserving HDL Design Hierarchy
.........12
H.-P.
Su,
A. C.-H. Wu and Y.-L·
Lin (Tsing Hua)
•
Nostradamus: A Floorplanner of Uncertain Design
........................................18
K. Bazargan, S. Kim andM. Sarrafzadeh (Northwestern)
Special Address
•
Impact of Web Technologies on EDA System Architectures
R. Newton (UCB)
Tutorial
•
Timing Metrics for Physical Design of Deep
Submicron
Technologies
...........................28
L
Pileggi (CMU), Moderator; J. Cong (UCLA), S. Otto (Intel) and A. Yang (Washington)
Special Address
•
Moore s Law and Physical Design ones
...............................................36
W. Maty (CMU)
Session
2:
Interconnect Optimization
Moderators: M. Alexander (Washington State)
Y.-L. Lin (Tsing
Hua)
VI
•
Greedy Wire-Sizing is Linear Time
..................................................39
С
C.-N.
Chu
and D. F. Wong (UT-Austin)
•
An Efficient Technique for Device and Interconnect Optimization in Deep
Submicron
Designs
..........45
J. Cong and
L
He (UCLA)
Special Address
•
Consorting with the
Consortia:
Cooperative Research for Fun and Profit
W. H. Joyner (SRC)
Session
3:
Layout Methodologies for RF Circuits
Moderator: M. Pedram
(USC)
W.
Dai (UCSC)
•
Device-Level Early Floorplanning Algorithms for RF Circuits
................................57
M. Aktuna, R. A.
Rutenbar
and
L R.
Carley (CMU)
•
A Layout Approach to Monolithic Microwave
1С.........................................65
A. Nagao, T. Kambe (SHARP); and I. Shirakawa (Osaka)
Session
4:
Framework and Benchmarks
Moderators: D. Hill (Synopsys)
L. Jones (Motorola)
•
CHDStd-Application Support for Reusable Hierarchical Interconnect Timing Views
.................75
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, A. Chokhavtia (Sematech);
D. Cottrell, D. Mallis (Silicon Integration Initiative); S. DasGupta and].
Morrelt
(IBM)
•
The ISPD Circuit Benchmark Suite
..................................................80
С
J. Alpert (IBM)
•
Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD
(in particular, PD) tools continue to serve as enablers
/
differentiators of technology in the future?
S. DasGupta (IBM), Moderator; R. Abrishami (Fujitsu Microelectronics), B. Beers (IBM),
D. Guiou
(Mentor Graphics), E. Hsieh
(Avant!),
J. Hutt (Synopsys), M. Khaira (Intel) and
L
Scheffer
(Cadence)
Session
5:
PD for Manufacturability
Moderators: M.
Wiesel
(Intel)
R.
Rutenbar
(CMU)
•
Critical Area Computation-A New Approach
...........................................89
E. Papadopoulou (IBM); and
D. T.
Lee (Northwestern)
•
Filling and Slotting: Analysis and Algorithms
...........................................95
VIÏ
Α. Β.
Kahng (UCLA);
G.
Robins, A. Singh (Virginia);
H. Wang
and A. Zelikovsky (UCLA)
Special Address
•
Global Wires: Harmful
..........................................................104
R. Otten
(Delfi)
Session
6:
Poster Presentations
Moderators: E. Yoffa (IBM)
G. Robins (Virginia)
•
Partioning
Using Second-Order
Information
and Stochastic-Gain Functions
.......................112
5.
Dutt (Ul-Chicago); and H. Theny (Intel)
•
A Parallel Algorithm for Zero Skew Clock Tree Routing
...................................118
Ζ
Xing and P. Banerjee (Northwestern)
•
On Convex Formulation of the Floorplan Area Minimization Problem
...........................124
T. Chen and M. Fan (Georgia Tech)
•
A Patten Matching Algorithm for Verification and Analysis of Very Large
1С
Layouts
................129
M. Niewcazas, W. Maty and A. Strojwas (CMU)
•
LIBRA~A Library-Independent Framework for Post-Layout Performance Optimization
...............135
R. Huang (UCSB);
Y. Wang (Avant!);
and K.-T. Cheng (UCSB)
•
Estimation of Maximum Current Envelope for Power Bus Analysis and Design
.....................141
S.
Bobba
and I.
N.
Hajj (Illinois)
•
New Efficient Algorithms for Computing Effective Capacitance
...............................147
A. B. Kahng (UCLA) and S. Muddu (SGI)
•
Calculation of Ramp Response of Lossy Transmission Lines Using Two-Port Network Functions
.........152
P. Heydari and M. Pedram
(USC)
•
Switch-Matrix Architecture and Routing for FPDs
........................................158
G.-M. WuandY.-W. Chang (Chiao-Tung)
Session
7:
Efficient Representation in Placement
Moderates: R. Otten (Delft)
C.
Sechen
(Washington)
•
Sequence-Pair Based Placement Method for Hard/Soft/Pre-placed Modules
.......................167
H.
Murata
and
E. S.
Kuh (UCB)
•
Rectilinear Block Placement using Permutation-Pair
.......................................173
/.
Xu, P. Guo and C.-K. Cheng (UCSD)
•
Topology Constrained Rectilinear Block Packing for Layout Reuse
............................179
M. Kang and W. Dai (UCSC)
•
Panel: Process development and its impact on Physical Design
...............................187
VIH
N.
Sherwani (Intel), Moderator; J. Cong (UCLA), D. LaPotin (IBM) and J.
Rey
(Cadence)
Tutorial
•
Futures for Partitioning in Physical Design
............................................190
A. B. Kahng (UCLA), Moderator;
C. J. Alpert
(IBM),
G. Janac (Cadence) andJ. Lillis (UI
-
Chicago)
Session
8:
Routing Algorithms
Moderators: J. Cong (UCLA)
J. Fishburn (Lucent)
•
Chip-Level Area Routing
.........................................................197
L.-C.
Liu, H.-P. Tseng and
С
Sechen
(Washington)
•
Routing Tree Topology Construction to Meet Interconnect Timing Constraints
......................205
H.
Hou
(Iowa State); and S. Sapatnekar (Minnesota)
•
Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips
...............................211
T. Stoehr, M. Alt (IBM); A. Hetzel (Bonn); andJ. Koehl (IBM)
Author Index
...................................................................219
IX
|
| any_adam_object | 1 |
| author_corporate | International Symposium on Physical Design Monterey, Calif |
| author_corporate_role | aut |
| author_facet | International Symposium on Physical Design Monterey, Calif |
| author_sort | International Symposium on Physical Design Monterey, Calif |
| building | Verbundindex |
| bvnumber | BV012037475 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75 |
| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)39104726 (DE-599)BVBBV012037475 |
| discipline | Informatik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01605nam a2200397 c 4500</leader><controlfield tag="001">BV012037475</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19981102 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">980702s1998 d||| |||| 10||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">158113021X</subfield><subfield code="9">1-58113-021-X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)39104726</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV012037475</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874.75</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 190f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">International Symposium on Physical Design</subfield><subfield code="n">2</subfield><subfield code="d">1998</subfield><subfield code="c">Monterey, Calif.</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5294784-1</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Proceedings</subfield><subfield code="b">ISPD-98 ; Monterey, CA, April 6-8, 1998</subfield><subfield code="c">1998 International Symposium on Physical Design</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">ISPD-98</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York</subfield><subfield code="b">ACM</subfield><subfield code="c">1998</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">IX, 220 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="v">Congresses</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008145491&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-008145491</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift gnd-content |
| genre_facet | Konferenzschrift |
| id | DE-604.BV012037475 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:20:32Z |
| institution | BVB |
| institution_GND | (DE-588)5294784-1 |
| isbn | 158113021X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-008145491 |
| oclc_num | 39104726 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | IX, 220 S. graph. Darst. |
| publishDate | 1998 |
| publishDateSearch | 1998 |
| publishDateSort | 1998 |
| publisher | ACM |
| record_format | marc |
| spelling | International Symposium on Physical Design 2 1998 Monterey, Calif. Verfasser (DE-588)5294784-1 aut Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 1998 International Symposium on Physical Design ISPD-98 New York ACM 1998 IX, 220 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Very large scale integration Congresses CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content VLSI (DE-588)4117388-0 s CAD (DE-588)4069794-0 s 1\p DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008145491&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 Integrated circuits Very large scale integration Congresses CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4069794-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 |
| title_alt | ISPD-98 |
| title_auth | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 |
| title_exact_search | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 |
| title_full | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 1998 International Symposium on Physical Design |
| title_fullStr | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 1998 International Symposium on Physical Design |
| title_full_unstemmed | Proceedings ISPD-98 ; Monterey, CA, April 6-8, 1998 1998 International Symposium on Physical Design |
| title_short | Proceedings |
| title_sort | proceedings ispd 98 monterey ca april 6 8 1998 |
| title_sub | ISPD-98 ; Monterey, CA, April 6-8, 1998 |
| topic | Integrated circuits Very large scale integration Congresses CAD (DE-588)4069794-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrated circuits Very large scale integration Congresses CAD VLSI Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008145491&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationalsymposiumonphysicaldesignmontereycalif proceedingsispd98montereycaapril681998 AT internationalsymposiumonphysicaldesignmontereycalif ispd98 |