HDL chip design: a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Madison, AL
Doone
1997
|
| Ausgabe: | 3. print., minor rev. |
| Schlagworte: | |
| Beschreibung: | XVI, 448 S. graph. Darst. |
| ISBN: | 0965193438 |
Internformat
MARC
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| 001 | BV011777983 | ||
| 003 | DE-604 | ||
| 005 | 19980318 | ||
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| 041 | |a und | ||
| 049 | |a DE-91G | ||
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| 084 | |a DAT 190f |2 stub | ||
| 100 | 1 | |a Smith, Douglas J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a HDL chip design |b a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |c Douglas J. Smith |
| 250 | |a 3. print., minor rev. | ||
| 264 | 1 | |a Madison, AL |b Doone |c 1997 | |
| 300 | |a XVI, 448 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 2 | |8 1\p |5 DE-604 | |
| 689 | 3 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 3 | |8 2\p |5 DE-604 | |
| 689 | 4 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 4 | |8 3\p |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007948759 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804126321125621760 |
|---|---|
| any_adam_object | |
| author | Smith, Douglas J. |
| author_facet | Smith, Douglas J. |
| author_role | aut |
| author_sort | Smith, Douglas J. |
| author_variant | d j s dj djs |
| building | Verbundindex |
| bvnumber | BV011777983 |
| classification_rvk | ST 250 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)634257967 (DE-599)BVBBV011777983 |
| discipline | Informatik |
| edition | 3. print., minor rev. |
| format | Book |
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| id | DE-604.BV011777983 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:15:35Z |
| institution | BVB |
| isbn | 0965193438 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007948759 |
| oclc_num | 634257967 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | XVI, 448 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Doone |
| record_format | marc |
| spelling | Smith, Douglas J. Verfasser aut HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith 3. print., minor rev. Madison, AL Doone 1997 XVI, 448 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 s DE-604 VHDL (DE-588)4254792-1 s Kundenspezifische Schaltung (DE-588)4122250-7 s 1\p DE-604 VERILOG (DE-588)4268385-3 s 2\p DE-604 Field programmable gate array (DE-588)4347749-5 s 3\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Smith, Douglas J. HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Kundenspezifische Schaltung (DE-588)4122250-7 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4159102-1 (DE-588)4347749-5 (DE-588)4268385-3 (DE-588)4254792-1 |
| title | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_auth | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_exact_search | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_full | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_fullStr | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_full_unstemmed | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_short | HDL chip design |
| title_sort | hdl chip design a practical guide for designing synthesizing and simulating asics and fpgas using vhdl or verilog |
| title_sub | a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| topic | Kundenspezifische Schaltung (DE-588)4122250-7 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Kundenspezifische Schaltung Hardwarebeschreibungssprache Field programmable gate array VERILOG VHDL |
| work_keys_str_mv | AT smithdouglasj hdlchipdesignapracticalguidefordesigningsynthesizingandsimulatingasicsandfpgasusingvhdlorverilog |