Computer aided design techniques for low power sequential logic circuits:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer Acad. Publ.
1997
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
387 |
| Schlagworte: | |
| Beschreibung: | XIII, 181 S. graph. Darst. |
| ISBN: | 0792398297 |
Internformat
MARC
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| 003 | DE-604 | ||
| 005 | 20030103 | ||
| 007 | t | ||
| 008 | 971209s1997 d||| |||| 00||| eng d | ||
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| 035 | |a (OCoLC)35688167 | ||
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| 084 | |a ELT 273f |2 stub | ||
| 100 | 1 | |a Monteiro, José |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Computer aided design techniques for low power sequential logic circuits |c José Monteiro and Srinivas Devadas |
| 246 | 1 | 3 | |a Computer-aided design techniques for low power sequential logic circuits |
| 264 | 1 | |a Boston [u.a.] |b Kluwer Acad. Publ. |c 1997 | |
| 300 | |a XIII, 181 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 387 | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Logic circuits |x Computer-aided design | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 4 | |a Low voltage integrated circuits |x Computer-aided design | |
| 650 | 0 | 7 | |a Reduktion |0 (DE-588)4177306-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Verlustleistung |0 (DE-588)4187881-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
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Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Monteiro, José Devadas, Srinivas 1963- |
| author_GND | (DE-588)121371107 |
| author_facet | Monteiro, José Devadas, Srinivas 1963- |
| author_role | aut aut |
| author_sort | Monteiro, José |
| author_variant | j m jm s d sd |
| building | Verbundindex |
| bvnumber | BV011677100 |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.L6 |
| callnumber-search | TK7868.L6 |
| callnumber-sort | TK 47868 L6 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 5630 |
| classification_tum | ELT 273f |
| ctrlnum | (OCoLC)35688167 (DE-599)BVBBV011677100 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV011677100 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:13:52Z |
| institution | BVB |
| isbn | 0792398297 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007871973 |
| oclc_num | 35688167 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | XIII, 181 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Kluwer Acad. Publ. |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Monteiro, José Verfasser aut Computer aided design techniques for low power sequential logic circuits José Monteiro and Srinivas Devadas Computer-aided design techniques for low power sequential logic circuits Boston [u.a.] Kluwer Acad. Publ. 1997 XIII, 181 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 387 Datenverarbeitung Logic circuits Computer-aided design Logic design Data processing Low voltage integrated circuits Computer-aided design Reduktion (DE-588)4177306-8 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Verlustleistung (DE-588)4187881-4 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 s Verlustleistung (DE-588)4187881-4 s Reduktion (DE-588)4177306-8 s CAD (DE-588)4069794-0 s DE-604 Devadas, Srinivas 1963- Verfasser (DE-588)121371107 aut The Kluwer international series in engineering and computer science 387 (DE-604)BV023545171 387 |
| spellingShingle | Monteiro, José Devadas, Srinivas 1963- Computer aided design techniques for low power sequential logic circuits The Kluwer international series in engineering and computer science Datenverarbeitung Logic circuits Computer-aided design Logic design Data processing Low voltage integrated circuits Computer-aided design Reduktion (DE-588)4177306-8 gnd Logische Schaltung (DE-588)4131023-8 gnd Verlustleistung (DE-588)4187881-4 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4177306-8 (DE-588)4131023-8 (DE-588)4187881-4 (DE-588)4069794-0 |
| title | Computer aided design techniques for low power sequential logic circuits |
| title_alt | Computer-aided design techniques for low power sequential logic circuits |
| title_auth | Computer aided design techniques for low power sequential logic circuits |
| title_exact_search | Computer aided design techniques for low power sequential logic circuits |
| title_full | Computer aided design techniques for low power sequential logic circuits José Monteiro and Srinivas Devadas |
| title_fullStr | Computer aided design techniques for low power sequential logic circuits José Monteiro and Srinivas Devadas |
| title_full_unstemmed | Computer aided design techniques for low power sequential logic circuits José Monteiro and Srinivas Devadas |
| title_short | Computer aided design techniques for low power sequential logic circuits |
| title_sort | computer aided design techniques for low power sequential logic circuits |
| topic | Datenverarbeitung Logic circuits Computer-aided design Logic design Data processing Low voltage integrated circuits Computer-aided design Reduktion (DE-588)4177306-8 gnd Logische Schaltung (DE-588)4131023-8 gnd Verlustleistung (DE-588)4187881-4 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Datenverarbeitung Logic circuits Computer-aided design Logic design Data processing Low voltage integrated circuits Computer-aided design Reduktion Logische Schaltung Verlustleistung CAD |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT monteirojose computeraideddesigntechniquesforlowpowersequentiallogiccircuits AT devadassrinivas computeraideddesigntechniquesforlowpowersequentiallogiccircuits |