Controller design from temporal logic: undecidability need not matter:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | German |
| Veröffentlicht: |
Kiel
Inst. für Informatik und Praktische Mathematik
1997
|
| Schriftenreihe: | Bericht / Institut für Informatik und Praktische Mathematik <Kiel>
9710 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 190 S. graph. Darst. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV011627999 | ||
| 003 | DE-604 | ||
| 005 | 20140716 | ||
| 007 | t | ||
| 008 | 971104s1997 gw d||| m||| 00||| ger d | ||
| 016 | 7 | |a 951730746 |2 DE-101 | |
| 035 | |a (OCoLC)75808202 | ||
| 035 | |a (DE-599)BVBBV011627999 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a ger | |
| 044 | |a gw |c DE | ||
| 049 | |a DE-91 |a DE-12 |a DE-355 |a DE-706 |a DE-188 | ||
| 084 | |a SK 130 |0 (DE-625)143216: |2 rvk | ||
| 084 | |a DAT 540d |2 stub | ||
| 084 | |a DAT 150d |2 stub | ||
| 100 | 1 | |a Fränzle, Martin |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Controller design from temporal logic: undecidability need not matter |c Martin Fränzle |
| 264 | 1 | |a Kiel |b Inst. für Informatik und Praktische Mathematik |c 1997 | |
| 300 | |a VIII, 190 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Bericht / Institut für Informatik und Praktische Mathematik <Kiel> |v 9710 | |
| 502 | |a Zugl.: Kiel, Univ., Diss., 1997 | ||
| 650 | 0 | 7 | |a Mikrocontroller |0 (DE-588)4127438-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Temporale Logik |0 (DE-588)4137542-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Systementwurf |0 (DE-588)4261480-6 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Mikrocontroller |0 (DE-588)4127438-6 |D s |
| 689 | 0 | 1 | |a Systementwurf |0 (DE-588)4261480-6 |D s |
| 689 | 0 | 2 | |a Temporale Logik |0 (DE-588)4137542-7 |D s |
| 689 | 0 | |5 DE-604 | |
| 810 | 2 | |a Institut für Informatik und Praktische Mathematik <Kiel> |t Bericht |v 9710 |w (DE-604)BV000011623 |9 9710 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007834879&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007834879 | |
Datensatz im Suchindex
| _version_ | 1807501420130205696 |
|---|---|
| adam_text |
CONTENTS
PREFACE
I
ACKNOWLEDGEMENTS
III
1
INTRODUCTION
1
2
WHY
CERTAIN
UNDECIDABILITY
RESULTS
NEED
NOT
MATTER
9
2.1
COMMON
PATTERNS
OF
UNDECIDABILITY
PROOFS
.
10
2.2
HOW
TO
EXPLOIT
THE
MISSING
PHYSICAL
INTERPRETATION
.
12
I
FORMAL
SPECIFICATION
OF
TIMED
BEHAVIOUR
13
3
MATHEMATICAL
NOTATION
15
3.1
RELATIONS
.
15
3.2
FUNCTIONS
.
15
3.3
STRINGS
.
16
3.4
ALMOST
UNIVERSAL
PROPERTIES
.
16
4
FUNDAMENTAL
MATHEMATICAL
MODELS
OF
REAL-TIME
SYSTEMS
17
4.1
TIME
.
18
4.2
STATE
SPACES
.
18
4.3
TRAJECTORIES
.
18
4.4
OBSERVATIONS
.
19
4.5
TIMED
REGULAR
EXPRESSIONS
.
19
5
DURATION
LOGIC
23
5.1
SYNTAX
.
23
5.1.1
STATE
VARIABLES
.
24
5.1.2
STATE
ASSERTIONS
.
24
5.1.3
DURATIONS
.
24
5.1.4
ATOMIC
DURATION
FORMULAE
.
25
5.1.5
DURATION
FORMULAE
.
25
5.2
SEMANTICS
.
27
CONTENTS
5.2.1
SATISFACTION
BY
FINITE
OBSERVATIONS
.
27
5.2.2
SATISFACTION
BY
INFINITE
TRAJECTORIES
.
30
5.2.3
SATISFIABILITY
AND
VALIDITY
.
30
5.3
DISCUSSION
.
31
6
DECIDABILITY
OF
DURATION
LOGIC
33
6.1
UNDECIDABILITY
ON
FINITELY
VARIABLE
MODELS
.
34
6.2
UNDECIDABILITY
ON
MODELS
OF
FINITELY
BOUNDED
VARIABILITY
.
35
6.3
DECIDABILITY
ON
TIME-WISE
DISCRETE
MODELS
.
41
6.4
DECIDABILITY
OF
OTHER
DURATION
CALCULI
ON
RESTRICTED
MODEL
CLASSES
.
51
6.4.1
SUBSET
{[P]}
.
51
6.4.2
SUBSET
{|\P],1
=
FC}
.
52
6.4.3
SUBSET
{
JP
=
JQ}
.
55
6.4.4
SUBSET
{[P],VA;,L
=
Z}
.
56
6.5
DISCUSSION
.
57
7
AUTOMATIC
VERIFICATION
AND
AUTOMATIC
SYNTHESIS
OF
CONTROLLER
DESIGNS
61
7.1
CONTROLLER
DESIGN
FROM
DURATION
LOGIC
SPECIFICATIONS
.
62
7.1.1
MODEL
CHECKING
.
63
7.1.2
AUTOMATIC
SYNTHESIS
.
63
7.2
TOWARDS
AUTOMATIC
PROCEDURES
FOR
DL-BASED
CONTROLLER
DESIGN
.
65
II
SYNTHESIS
OF
SYNCHRONOUS CONTROLLERS
67
8
SYNTHESIZING
SYNCHRONOUS
CONTROLLERS
FROM
DL
SPECIFICATIONS
69
8.1
SYNCHRONOUSLY
CLOCKED
CONTROLLERS
.
70
8.2
A
NON-STANDARD
INTERPRETATION
OF
CLOCKED
CONTROLLERS
.
72
8.3
A
WEAKER
REFINEMENT
CRITERION
THAN
TRAJECTORY
INCLUSION
.
79
8.3.1
THE
WEAKER
CRITERION
IN
TERMS
OF
THE
NON-STANDARD
SEMANTICS
.
81
8.4
DISCUSSION
.
84
9
THE
GAS-BURNER:
AN
EXAMPLE
OF
AUTOMATIC
CONTROLLER
SYNTHESIS
FROM
DURATION
LOGIC
87
9.1
THE
REQUIREMENTS
SPECIFICATION
.
88
9.2
DERIVING
THE
CASE
AUTOMATON
.
90
9.3
SYNTHESIS
OF
THE
SYNCHRONOUS
CONTROLLER
.
92
9.4
DISCUSSION
.
95
III
KEY-PRESS
VERIFICATION
OF
ASYNCHRONOUS
CIRCUITS
99
10
TEST
PREORDER
AND
REFINEMENT
101
10.1
OBSERVATION-ORIENTED
SEMANTICS
AND
REFINEMENT
IN
ENGINEERING
.
101
10.2
TESTING
AND
ITS
PREORDERS
IN
A
DENOTATIONAL
SETTING
.
104
CONTENTS
10.3
TESTING-ADEQUATE
REFINEMENT
RELATIONS
.
109
10.4
COMPILING
CORRECTNESS
.
110
10.5
DISCUSSION
.
114
11
HYBRID
DURATION
LOGIC
117
11.1
SYNTACTIC
EXTENSIONS
.
117
11.1.1
PIECEWISE
CONTINUOUS
STATE
VARIABLES
AND
EXPRESSIONS
.
118
11.1.2
INTEGRALS
OVER
TIME
.
119
11.1.3
INITIAL
AND
FINAL
VALUES
.
119
11.1.4
INTEGRAL
AND
BOUNDARY
VALUE
EXPRESSIONS
.
119
11.1.5
INTEGRAL
EQUATIONS
AND
INEQUATIONS
.
119
11.1.6
EXISTENTIAL
QUANTIFICATION
OF
TIME-DEPENDENT
STATES
.
120
11.2
SEMANTICS
.
120
11.2.1
SATISFACTION
BY
FINITE
OBSERVATIONS
.
121
11.3
SATISFACTION,
VALIDITY,
AND
LOGICAL
CONSEQUENCE
.
123
11.4
DISCUSSION
.
124
12
A
DISCRETE-STATE
MODEL
OF
VLSI
DYNAMICS
IN
EMBEDDED
CONTROL
125
12.1
SYNCHRONIZATION
FAILURE
.
125
12.2
A
SIMPLE
HARDWARE
LANGUAGE
.
127
12.3
A
DESIGN-LEVEL
MODEL
IN
HDL
.
129
12.3.1
RELATION
TO
SWITCHING
THEORY
.
131
12.4
CMOS
TECHNOLOGY
.
131
12.4.1
NMOS
ENHANCEMENT
MODE
TRANSISTOR
.
131
12.4.2
PMOS
ENHANCEMENT
MODE
TRANSISTOR
.
132
12.4.3
CMOS
NAND
GATE
.
133
12.4.4
SENSORS
AND
ACTUATORS
.
136
12.4.5
CONNECTING
CMOS
DEVICES
TO
FORM
LARGER
CIRCUITS
.
136
12.4.6
HIDING
INTERNAL
NODES
OF
CIRCUITS
.
137
12.4.7
COMPLETE
SYSTEM
.
137
12.5
SOUNDNESS
OF
THE
DESIGN
MODEL
WITH
RESPECT
TO
CIRCUIT-LEVEL
DYNAMICS
.
138
12.5.1
SUCCESS
CRITERIA
.
138
12.5.2
SATISFACTION
OF
EXPECTATIONS
BY
COMPLETE
SYSTEMS
.
138
12.5.3
CMOS
IMPLEMENTATION
OF
THE
SIMPLE
HARDWARE
LANGUAGE
.
139
12.5.4
VERIFICATION
OF
COMPILATION
TO
CMOS
CIRCUITRY
.
140
12.6
DISCUSSION
.
145
12.6.1
RELATED
WORK
ON
HARDWARE
VERIFICATION
.
146
13
DECIDABILITY
FOR
FREE:
CORRECTNESS
OF
GATE-LEVEL
DESIGNS
149
13.1
POSTULATING
BOUNDED
VARIABILITY
.
150
13.2
DECIDABILITY
OF
CIRCUIT
CORRECTNESS
.
157
13.3
DISCUSSION
.
159
CONTENTS
14
CONCLUSIONS
163
14.1
SUMMARY
OF
RESULTS
.
163
14.2
FURTHER
RESEARCH
.
166
14.2.1
LIVENESS
AND
FAIRNESS
IN
DURATION
CALCULI
.
167
14.2.2
APPLICATION
TO
OTHER
TEMPORAL
LOGICS
.
167
14.2.3
NON-BOOLEAN
REQUIREMENTS
.
168
14.3
POSSIBLE
EXPLOITATION
.
168
14.3.1
AUTOMATIC
HARDWARE
SYNTHESIS
.
168
14.3.2
AUTOMATIC
VERIFICATION
AND
AUTOMATIC
SYNTHESIS
OF
EMBEDDED
CONTROL
SOFTWARE
.
169
14.3.3
SEMANTICS
OF
HIGH-LEVEL
HARDWARE
DESCRIPTION
LANGUAGES
.
170
BIBLIOGRAPHY
171
A
ENCODING
TIMED
AUTOMATA
WITH
STOP-WATCHES
IN
DURATION
LOGIC
179
A.L
ENCODING
REACHABILITY
PROBLEMS
.
179
A.2
UNDECIDABILITY
RESULTS
.
185
A.3
DISCUSSION
.
186
INDEX
187 |
| any_adam_object | 1 |
| author | Fränzle, Martin |
| author_facet | Fränzle, Martin |
| author_role | aut |
| author_sort | Fränzle, Martin |
| author_variant | m f mf |
| building | Verbundindex |
| bvnumber | BV011627999 |
| classification_rvk | SK 130 |
| classification_tum | DAT 540d DAT 150d |
| ctrlnum | (OCoLC)75808202 (DE-599)BVBBV011627999 |
| discipline | Informatik Mathematik |
| format | Thesis Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV011627999</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20140716</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">971104s1997 gw d||| m||| 00||| ger d</controlfield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">951730746</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)75808202</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV011627999</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">ger</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">DE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-12</subfield><subfield code="a">DE-355</subfield><subfield code="a">DE-706</subfield><subfield code="a">DE-188</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">SK 130</subfield><subfield code="0">(DE-625)143216:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 540d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 150d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Fränzle, Martin</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Controller design from temporal logic: undecidability need not matter</subfield><subfield code="c">Martin Fränzle</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Kiel</subfield><subfield code="b">Inst. für Informatik und Praktische Mathematik</subfield><subfield code="c">1997</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">VIII, 190 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Bericht / Institut für Informatik und Praktische Mathematik <Kiel></subfield><subfield code="v">9710</subfield></datafield><datafield tag="502" ind1=" " ind2=" "><subfield code="a">Zugl.: Kiel, Univ., Diss., 1997</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mikrocontroller</subfield><subfield code="0">(DE-588)4127438-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Temporale Logik</subfield><subfield code="0">(DE-588)4137542-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Systementwurf</subfield><subfield code="0">(DE-588)4261480-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Mikrocontroller</subfield><subfield code="0">(DE-588)4127438-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Systementwurf</subfield><subfield code="0">(DE-588)4261480-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Temporale Logik</subfield><subfield code="0">(DE-588)4137542-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="810" ind1="2" ind2=" "><subfield code="a">Institut für Informatik und Praktische Mathematik <Kiel></subfield><subfield code="t">Bericht</subfield><subfield code="v">9710</subfield><subfield code="w">(DE-604)BV000011623</subfield><subfield code="9">9710</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007834879&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007834879</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV011627999 |
| illustrated | Illustrated |
| indexdate | 2024-08-16T00:21:19Z |
| institution | BVB |
| language | German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007834879 |
| oclc_num | 75808202 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-12 DE-355 DE-BY-UBR DE-706 DE-188 |
| owner_facet | DE-91 DE-BY-TUM DE-12 DE-355 DE-BY-UBR DE-706 DE-188 |
| physical | VIII, 190 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Inst. für Informatik und Praktische Mathematik |
| record_format | marc |
| series2 | Bericht / Institut für Informatik und Praktische Mathematik <Kiel> |
| spelling | Fränzle, Martin Verfasser aut Controller design from temporal logic: undecidability need not matter Martin Fränzle Kiel Inst. für Informatik und Praktische Mathematik 1997 VIII, 190 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Bericht / Institut für Informatik und Praktische Mathematik <Kiel> 9710 Zugl.: Kiel, Univ., Diss., 1997 Mikrocontroller (DE-588)4127438-6 gnd rswk-swf Temporale Logik (DE-588)4137542-7 gnd rswk-swf Systementwurf (DE-588)4261480-6 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Mikrocontroller (DE-588)4127438-6 s Systementwurf (DE-588)4261480-6 s Temporale Logik (DE-588)4137542-7 s DE-604 Institut für Informatik und Praktische Mathematik <Kiel> Bericht 9710 (DE-604)BV000011623 9710 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007834879&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Fränzle, Martin Controller design from temporal logic: undecidability need not matter Mikrocontroller (DE-588)4127438-6 gnd Temporale Logik (DE-588)4137542-7 gnd Systementwurf (DE-588)4261480-6 gnd |
| subject_GND | (DE-588)4127438-6 (DE-588)4137542-7 (DE-588)4261480-6 (DE-588)4113937-9 |
| title | Controller design from temporal logic: undecidability need not matter |
| title_auth | Controller design from temporal logic: undecidability need not matter |
| title_exact_search | Controller design from temporal logic: undecidability need not matter |
| title_full | Controller design from temporal logic: undecidability need not matter Martin Fränzle |
| title_fullStr | Controller design from temporal logic: undecidability need not matter Martin Fränzle |
| title_full_unstemmed | Controller design from temporal logic: undecidability need not matter Martin Fränzle |
| title_short | Controller design from temporal logic: undecidability need not matter |
| title_sort | controller design from temporal logic undecidability need not matter |
| topic | Mikrocontroller (DE-588)4127438-6 gnd Temporale Logik (DE-588)4137542-7 gnd Systementwurf (DE-588)4261480-6 gnd |
| topic_facet | Mikrocontroller Temporale Logik Systementwurf Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007834879&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000011623 |
| work_keys_str_mv | AT franzlemartin controllerdesignfromtemporallogicundecidabilityneednotmatter |