Proceedings 1997: Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997
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| Format: | Tagungsbericht Buch |
| Sprache: | English |
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Piscataway, NY
IEEE
1997
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIX, 788 S. Ill., graph. Darst. |
| ISBN: | 0897919203 0780340930 0780340949 |
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| 111 | 2 | |a Design Automation Conference (Association for Computing Machinery) |n 34 |d 1997 |c Anaheim, Calif. |j Verfasser |0 (DE-588)5251559-X |4 aut | |
| 245 | 1 | 0 | |a Proceedings 1997 |b Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 |c 34th Design Automation Conference |
| 264 | 1 | |a Piscataway, NY |b IEEE |c 1997 | |
| 300 | |a XXIX, 788 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| adam_text |
Table
of
Contents
General Chair's Welcome
.
iii
Executive Committee
.iv
Technical Program Committee
.vi
1997
Best Paper Award
.ix
ACSEE Undergraduate Scholarships
.ix
Design Automation Conference Graduate Scholarship Awards
.
χ
35th Call for Papers
.xi
SIGDA Meritorious Service Award
.xi
Reviewers
.xii
Opening Keynote Address
—
Scott
G
.
McNealy
.xvi
Thursday Keynote Address
—
Michael
A. Aymar
.xvii
Panel: An Executive View of the EDA Industry
Chair: A. Richard Newton
Organizer: Mike Murray
Panel Members: Joseph
Costello,
Aart de Geus,
William
Herman,
Gerald Hsu,
Keith
Lobo,
Walden
Rhines
.1
Session
1
Sequential Synthesis
Chair: Richard L. Rudell
Organizers:
Fabio Somenzi,
Sharad Malik
1.1
An Improved Algorithm for Minimum-Area Retiming
Naresh Maheshwari,
Sachin
S.
Sapatnekar
.,.2
1.2
Efficient Latch Optimization Using Exclusive Sets
Ellen
M
.
Sentovich,
Horia
Toma,
Gerard Berry
.8
1.3
Sequence Compaction for Probabilistic Analysis of Finite-State Machines
Diana
Marculescu, Radu Marculescu,
Massoud Pedram
.12
1.4
Synthesis of Speed-Independent Circuits from STG-unfolding Segment
Alexei Semenov,
Alexandre Yakovlev,
Enríe
Pastor, Marco
A. Peña, Jordi
Cortadella
.16
1.5
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive
Latency Control
Luca
Benini,
Enrico
Macii,
Massimo
Pancino.
22
Session
2
Interconnect Modeling
Chair: Lawrence T. Pileggi
Organizers: Andrew T. Yang, Jacob White
2.1
Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks
Ibrahim M. Elfadel, David D. Ling
.28
2.2
Preservation of Passivity During RLC Network Reduction via Split Congruence
Transformations
Kevin J. Kerns, Andrew T. Yang
.34
2
J
Lumped Interconnect Models Via Gaussian Quadrature
Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S.
Kundért,
Jacob K. White
.40
2.4
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling
Florentin
Dartu, Lawrence T. Pileggi
.46
xviii
Session 3
Novel Techniques for Software Scheduling
Chairs: Gaetano Borriello, Nikil Dutt
Organizers: Rajesh K. Gupta, Luciano Lavagno
3.1
Schedule Validation for Embedded Reactive Real-Time Systems
Felice Balarin, Alberto Sangiovanni-Vincentelli
.52
3.2
Incorporating Imprecise Computation into System-Level Design of Application-Specific
Heterogeneous Multiprocessors
YosefG. Tirat-Gefen, Diogenes
С
Silva,
Alice
С.
Parker
.58
3.3
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA
Targets
Marleen
Ade,
Rudy
Lauw
ereins,
J. A.
Peperstraete
.64
3.4
An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design
Environment
Stan Liao, Steve Tjiang, Rajesh Gupta
.70
Session
4
4.1
Embedded Tutorial: Tools and Methodologies for Low Power Design
Jerry Frenkil
.76
Panel: Low-Power Design Tools
—
Where Is the Impact?
Chair: Jan M. Rabaey
Organizer: Nanette Collins
Panel Members: Bill Bell, Jerry Frenkil, Vassilios Gerousis, Massoud Pedram,
Deo Singh, Jim
Šproch
.82
Session
5
Simulation Techniques for Microprocessors
Chair: Haruyuki Tago
Organizers: Haruyuki Tago,
Neil Weste
5.1
A
С
-Based
RTL
Design Verification Methodology for Complex Microprocessor
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park,
Hoon
Choi, Woo-Seung Yang,
Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung
.83
5.2
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS
Multiprocessors
Jörg
Walter, Jens Leenstra, Gerhard
Döttling, Bernd Leppla, Hans-Jürgen Münster,
Kevin
Kark,
Bruce Wile
.89
5.3
Efficient Testing of Clock Regenerator Circuits in Scan Designs
Rajesh
Raina,
Robert Bailey, Charles Njinda, Robert Molyneaux, Charlie
Beh
.95
5.4
A Real-Time
RTL
Engineering-Change Method Supporting On-Line Debugging for
Logic-Emulation Applications
Wen-Jong Fang, Allen C.-H. Wu,
Τι
-Yen
Yen
.101
Session
6
Combinational Logic Synthesis
Chair:
Hamid
Savoj
Organizers: Andreas Kuehlmann, Massoud Pedram
6.1
A Graph-Based Synthesis Algorithm for AND/XOR Networks
Yibin Ye, KaushikRoy
.107
6.2
Optimizing Designs Containing Black Boxes
Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal
.¡13
6.3
Solving Covering Problems Using LPR-Based Lower Bounds
Stan Liao, Srinivas Devadas
.117
6.4
Exact Coloring of Real-Life Graphs is Easy
Olivier Coudert
.121
Session
7
Interconnect Parasitic Extraction
Chair: Andrew T. Yang
Organizers: Jacob White, Jason Cong
7.1
Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect
Modeling
E. Aykut Dengi, Ronald A. Rohrer
.127
7.2
Bounds for
BEM
Capacitance Extraction
Michael W. Beanie, Lawrence T. Pileggi
.133
7.3
SPIE:
Sparse Partial Inductance Extraction
Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
.137
7.4
A Fast Method of Moments Solver for Efficient Parameter Extraction of MCMs
Sharad Kapur, Jinsong Zhao
.141
Session
8
Advances in Timing Analysis for Embedded Software
Chairs: Wendell Baker, Hiroto Yasuura
Organizers: Rajesh K. Gupta, Luciano Lavagno
8.1
Embedded Tutorial: Static Timing Analysis of Embedded Software
Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li
.147
8.2
A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors
YanbingLi, Wayne Wolf.
.753
8.3
Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded
Systems
Rajeshkumar Sambandam, Xiaobo (Sharon)
Ни
.157
Session
9
Applications of Formal Verification
Chair: Andreas Kuehlmann
Organizers: Haruyuki Tago,
Neil Weste
9.1
Formal Verification of a Superscalar Execution Unit
Kyle L. Nelson, AlokJain, Randal E. Bryant
.161
9.2
Formal Verification of Content Addressable Memories Using Symbolic Trajectory
Evaluation
Manish Pandey, Richard Raimi, Randal E. Bryant,
Magdy
S. Abadir
.767
9.3
Formal Verification of FIRE: A Case Study
Jae-Young Jang, Shaz Qadeer, Matt
Kaufmann, Carl
Pixley
.173
Session
10
System-Level Exploration and Refinement
Chair:
Ivo Bolsens
Organizers:
Ivo
Bolsens, Anders
Forsen
10.1
Interface-Based Design
James A. Rowson, Alberto Sangiovanni-Vincentelli
.178
10.2
An Integrated Design Environment for Performance and Dependability Analysis
Robert H. Klenke,
Moshe
Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao,
Anup Ghosh
.¡84
xx
10.3
A Dynamic Design Estimation and Exploration Environment
Ole
Bentz, JanM. Rabaey, David B.
Lidsky
.¡90
Session
11
Binary Decision Diagrams
Chair: Andreas Kuehlmann
Organizers: Massoud Pedram, Andreas Kuehlmann
11.1
Remembrance of Things Past: Locality and Memory in BDDs
Srilatha
Manne,
Dirk
Grunwald,
Fabio Somenzi
.196
11.2
Linear Sifting of Decision Diagrams
Christoph
Meinel,
Fabio
Somenzi,
Thorsten
Theobald
.202
11.3
Safe BDD Minimization Using Don't Cares
Youpyo Hong, Peter
A. Beerei,
Jerry
R.
Burch, Kenneth L. McMillan
.208
Session
12
Timing Analysis
Chair:
Karem
A. Sakallah
Organizers:
Karem
A. Sakallah, Sharad Malik
12.1
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater
Insertion
John Lillis, Chung-Kuan Cheng
.214
12.2
Exact Required Time Analysis via False Path Detection
Yuji Kukimoto, Robert K. Brayton
.220
12.3
Symbolic Timing Verification of Timing Diagrams using
Presburger
Formulas
Tod
Amon,
Gaetano
Bordello,
Taokuan
Hu, Jiwen
Liu
.226
Session
13
13.1
Embedded Tutorial: Code Generation for Core Processors
Chair: Rajesh Gupta
Organizer: Giovanni
De Micheli
Presenter: Peter Marwedel
.232
Session
14
Panel: Physical Design and Synthesis: Merge or Die!
Chair: Massoud Pedram
Organizer: Massoud Pedram
Panel Members: Richard Bushroe, Raul Camposano, Giovanni
De Micheli,
Antun
Domic,
Chi-Ping Hsu, Michael Jackson
.238
Session
15
System-Level Optimization and Verification
Chair: Jeff Haight
Organizers:
Ivo Bolsens,
James A. Rowsen
15.1
Interface Timing Verification Drives System Design
Ajay J.
Daga,
Peter R. Suaris
.240
15.2
Memory-CPU Size Optimization for Embedded System Designs
Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama,
Hiroto Yasuura
.246
15.3
Methodology for Behavioral Synthesis-based Algorithm-level Design Space Exploration:
DCT Case Study
Miodrag Potkonjak, Kyosun Kim, Ramesh Karri
.252
Session 16
Formal
Verification
Chair:
Fabio Somenzi
Organizers:
Fabio Somenzi, Giovanni De Micheli
16.1
Embedded Tutorial: Formal Verification in a Commercial Setting
R. P. Kurshan
.258
16.2
Equivalence Checking Using Cuts and Heaps
Andreas Kuehlmann,
Florian
Krohm
.263
Session
17
Analog Simulation
Chair: Giorgio Casinovi
Organizers: Jacob White, Hidetoshi Onodera
17.1
Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits
Jaijeet Roychowdhury
.269
17.2
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances
Michael W.
Tian,
C.-J. Richard Shi
.275
17.3
SWITTEST: Automatic Switch-level Fault Simulation and Test Evaluation of Switched-
Capacitor Systems
S. Mir,
A. Rueda,
T.
Olbrich,
E. Peralias,
J. L.
Huertas.
281
Session
18
Software Synthesis for Embedded Systems
Chair: Sharad Malik
Organizers: Sharad Malik, Luciano Lavagno
18.1
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP
Architectures
Ashok Sudarsanam, Stan Liao, Srinivas Devadas
.287
18.2
System Level Fixed-Point Design Based on an Interpolative Approach
Markus
Willems, Volker Bürsgens,
Holger Keding,
Thorsten Grötker,
Heinrich Meyr
.293
18.3
ISDL:
An Instruction Set Description Language for Retargetability
George Hadjiyiannis, Silvina Hanono, Srinivas Devadas
.299
18.4
Generation of Software
Tools from
Processor
Descriptions for
Hardware/Software
Codesign
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai,
Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar
.303
Session
19
Experiences in
System Design
and Education at Universities
Chairs: Jan
M.
Rabaey, Anantha Chandrakasan
Organizer: Jan
M.
Rabaey
19.1
Education
for the Deep
Submicron Age:
Business As Usual?
Hugo
De
Man
.307
19.2
INFOPAD
—
An Experiment in System-Level Design and Integration
Robert W. Brodersen
.313
19.3
Very Rapid Prototyping of Wearable Computers: A Case Study of Custom Versus
Off-the-Shelf Design Methodologies
Asim Smailagic, Daniel P. Siewiorek, Richard Martin, John Stivoric
.315
Session 20
Standard
Cell and Physical Design Methods
Chair:
Neil Weste
Organizers:
Neil Weste,
Randolph E.
Harr
20.1
CAD at the Design-Manufacturing Interface
H. T.
Heineken,
J.
Khare,
W.
Maly, P.
К.
Nag,
С.
Ouyang,
W. A. Pleskacz
.321
20.2
CELLERITY: A
Fully Automatic Layout Synthesis System for Standard Cell Libraries
Mohan Guruswamy, Robert
L
Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri,
Andrea Fernandez, Larry G. Jones
.327
20.3
Developing a Concurrent Methodology for Standard-Cell Library Generation
Donald G. Baltus, Thomas
Varga,
Robert
С
Armstrong, John
Duh,
T. G. Matheson
.333
20.4
A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis
John
F. Croix,
D. F.
Wong
.337
Session
21
Modeling and Transformations in Synthesis
Chair: David Ku
Organizers: Kazutoshi Wakabayashi, Raul Camposano
21.1
Limited Exception Modeling and Its Use in Presynthesis Optimization
Jian
Li, Rajesh K. Gupta
.341
21.2
Potential-Driven Statistical Ordering of Transformations
Inki
Hong, Darko Kirovski, Miodrag Potkonjak
.347
21.3
Synthesis of Application Specific Programmable Processors
Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
.353
21.4
Symbolic Evaluation of Performance Models for Tradeoff Visualization
Jeffrey Walrath,
Ranga Vemuri
.359
Session
22
Statistical Power Estimation Techniques
Chair:
Luca
Benini
Organizers: Massoud Pedram, Andrew T. Yang
22.1
Power Macromodeling for High Level Power Estimation
Subodh Gupta, Farid
N.
Najm
.365
22.2
Statistical Estimation of the Cumulative Distribution Function for Power Dissipation
in VLSI Circuits
Chih-Shun Ding, Qing Wu, Cheng
-Та
Hsieh, Massoud Pedram
.371
22.3
Statistical Estimation of Average Power Dissipation in Sequential Circuits
Li
-Реп
Yuan, Chin-Chi
Teng, Sung-Mo
Kang
.377
22.4
Vector Generation for Maximum Instantaneous Current Through Supply Lines for
CMOS Circuits
Angela
Krstić,
Kwang-Ting (Tim) Cheng
.383
Session
23
Co-Simulation
Chair: Kunle Olukotun
Organizers: Rajesh K. Gupta, Kunle Olukoton
23.2
Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis
Claudio Passerone,
Luciano Lavagno, Massimiliano
Chiodo,
Alberto Sangiovanni-Vincentelli
.389
23.3
Dynamic Communication Models in Embedded System Co-Simulation
Ken Hines, Gaetano Borriello
.395
ХХШ
Session 24
Panel:
Challenges
in
Worldwide
IP
Reuse
with Embedded Tutorial:
Applying VSIA Standards to System on Chip Design
Chair: Rita Glover
Organizers: Takahide Inoue, Rita Glover, John
Teets
Panel Members: Doug Fairbairn, Larry Cooke, Steve
Schulz,
Takahide Inoue,
Raj Raghavan, Jean-Louis Bories,
Wally Rhines.401
Session
25
Emerging Technologies and Architectures for Low Power
Chair: Vivek Tiwari
Organizers: Anatha
Chandrakasan,
Robert
C. Frye
25.1
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS
Random Logic Networks
Pankaj Pant, Vivek
De, Abhijit
Chatterjee
.403
25.2
Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology
James
Kao,
Anantha
Chandrakasan,
Dimitri
Antoniadis
.409
25.3
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study
of the
ГОСТ
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha
Chandrakasan.415
25.4
A Power Estimation Framework for Designing Low Power Portable Video Applications
Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram
.421
25.5
An Investigation of Power Delay Trade-Offs on PowerPC Circuits
Qi Wang,
Sarma
В. К.
Vrudhula,
Shantanu
Ganguly
.425
Session
26
High Level Synthesis for Low Power
Chair: Kazutoshi Wakabayashi
Organizers: Raul Camposano, Kazutoshi Wakabayashi
26.1
Power Management Techniques for Control-Flow Intensive Designs
Anand Raghunathan,
S
ujit
Dey,
Niraj
К.
Jha, Kazutoshi Wakabayashi
.429
26.2
Low Energy Memory and Register Allocation Using Network Flow
Catherine H. Gebotys
.435
26.3
Power-Conscious High Level Synthesis Using Loop Folding
Daehong Kim, Kiyoung Choi
.441
Session
27
Module Generation
Chair: Dwight D. Hill
Organizers:
Antun
Domic, Patrick Groeneveld
27.1
Embedded Tutorial: The Future of Custom Cell Generation in Physical Synthesis
Martin Lefebvre, David Marple,
Carl Sechen.446
27.2
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
Avaneendra Gupta, John P. Hayes
.452
27.3
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design
Jaewon Kim,
S. M. Kong
.456
27.4
Technology Retargeting for
1С
Layout
John
Lakos
.460
XXIV
Session 28
BIST and DFT
Chair: Yervant
Zorian
Organizers:
Janusz Rajski,
Yervant Zorian
28.1
A Test Synthesis Approach to Reducing BALLAST DFT Overhead
Douglas Chang, Mike Tien-Chien Lee,
Małgorzata Marek-Sadowska,
Takashi Aikyo,
Kwang-Ting Cheng
.466
28.2 STARBIST: Scan
Autocorrelated Random Pattern Generation
K. H. Tsai, S.
Hellebrand,
J.
Rajski,
M. Marek-Sadowska
.472
28.3
A
Hybrid
Algorithm for Test Point Selection for Scan-Based BIST
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
.478
Session
29
Panel: Hardware/Software Co-Verification
Chair: Gary Smith
Organizers: Michel Courtoy, Marion Kenefick
Panel Members: Brian Bailey, Kurt Keutzer, Amr Mohsen, Richard Moseley, Jim Rowson,
Geoff Bunza, Willis Hendley
.484
Session
30
DSP
&
Telecommunication System Design
Chair: Rajeev Jain
Organizers: Phil Duncan, Teresa
Meng
30.1
Design and Synthesis of Array Structured Telecommunication Processing Applications
Wolfgang Meyer, Andrew Seawright, Fumiya
Tada
.486
30.2
RASSP Virtual Prototyping of DSP Systems
С
Hein,
J.
Pridgen,
W.
Kline
.492
30.3
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
Claus
Schneider
.498
Session
31
31.1
Embedded Tutorial: High-Level Power Modeling, Estimation, and Optimization
Chair: Massoud Pedram
Organizers: Giovanni
De Micheli,
Massoud Pedram
Presenters: Enrico
Macii,
Massoud Pedram,
Fabio Somenzi
.504
Session
32
Advances in Partitioning
Chair: Martin D. F. Wong
Organizers:
Antun
Domic, Patrick Groeneveld
32.1
A Network Flow Approach for Hierarchical Tree Partitioning
Ming
-Тег
Kuo, Chung-Kuan Cheng
.512
32.2
Multi-
Way FPGA Partitioning by Fully Exploiting Design Hierarchy
Wen-Jong Fang, Allen C.-H. Wu
.518
32.3
A Hierarchy-Driven FPGA Partitioning Method
Helena Krupnova,
Ali Abbara, Gabriele
Saucier
.522
32.4
Multilevel Hypergraph Partitioning: Application in VLSI Domain
George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar
.526
32.5
Multilevel Circuit Partitioning
Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
.530
Session 33
Processor
Test
Techniques
Chair:
Janusz Rajski
Organizers: Yervant Zorian,
Janusz Rajski
33.1
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
.534
33.2
Frequency-Domain Compatibility in Digital Filter BIST
Laurence Goodby, Alex Orailoglu
.540
33.3
A Scheme for Integrated Controller-Datapath Fault Testing
M. Nourani, J.
Carletta, C. Papachristou
.546
Session
34
Panel: The Next Generation HDL
Chair: Steven E.
Schulz
Organizers: Richard Goering, Nanette Collins
Panel Members: Gerard Berry, Kurt Keutzer, Maq
Mannan,
James A. Rowson,
Alberto Sangiovanni-Vincentelli, Larry Sounders
.552
Session
35
Design Processes and Frameworks
Chair: Teresa
Meng
Organizers: Teresa
Meng, Jan M.
Rabaey
35.1
Executable Workflows: A Paradigm for Collaborative Design on the Internet
Hemang Lavana,
Amit
Khetawat, Franc Brglez,
Krzysztof
Kozminski
.553
35.2
Electronic Component Information Exchange (ECIX)
Donald R. Cottrell
.559
35.3
Modeling Design Tasks and Tools
-
The Link Between Product and Flow Model
Bernd Schürmann,
Joachim
Altmeyer.564
Session
36
Probabilistic Models of Input Data for Efficient Power Estimation
Chair: Farid
N.
Najm
Organizers:
Fabio
Somenzi, Andrew T. Yang
36.1
Hierarchical Sequence Compaction for Power Estimation
Radu Marculescu,
Diana Marculescu, Massoud Pedram
.570
36.2
Profile-Driven Program Synthesis for Evaluation of System Power Dissipation
Cheng
-Ία
Hsieh, Massoud Pedram, Gaurav Mehta, Fred Rastgar
.576
363
Analytical Estimation of Transition Activity from Word-Level Signal Statistics
Sumant Ramprasad,
Nares
h R.
Shanbhag, Ibrahim
N.
Hajj
.582
Session
37
Hot Topics in Routing
Chair:
Carl Sechen
Organizers: Patrick Groeneveld,
Antun
Domic
37.1
Wire Segmenting for Improved Buffer Insertion
Charles Alpert, Anirudh Devgan
.588
37.2
More Practical Bounded-Skew Clock Routing
Andrew B. Kahng, C.-W. Albert Tsao
.594
37.3
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via
Minimization
Chin-Chih Chang, Jason Cong
.600
XXVI
37.4 Optimal
Wire-Sizing Function with Fringing Capacitance Consideration
Chung-Ping Chen, D.
F
Wong
.604
Session
38
Test Generation and Fault Simulation
Chair: Vishwani Agrawal
Organizers: Yervant Zorian,
Janusz Rajski
38.1
Fault Simulation Under the Multiple Observation Time Approach Using Backward
Implications
Irith Pomeranz, Sudhakar M. Reddy
.608
38.2
ATPG for Heat Dissipation Minimization during Scan Testing
Seongmoon Wang, Sandeep K. Gupta
.614
38.3
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits
Oriol
Roig, Jordi Cortadella, Marco
A. Peña, Enric
Pastor
.620
Session
39
Panel: The Road Ahead in CPLD
&
FPGA Design Methodology
Chair: Rhondalee Rohleder
Organizer: John Birkner
Panel Members: Don
Faria,
Steve Golson, Robert K. Beachler, Bruce
Kleinman,
Mike
Dini,
Bob Donaldson, Dave Kohlmeier.
.626
Session
40
Deep
Submicron
Modeling and Analysis
Chair: Robert C. Frye
Organizers: Vivek Tiwari, Anantha
Chandrakasan
40.1
Analysis and Justification of a Simple, Practical
2
1/2-D Capacitance Extraction
Methodology
Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali,
Steve H.-C. Yen
.627
40.2
Accurate and Efficient
Macromodel
of
Submicron
Digital Standard Cells
Cristiano Forzan,
Bruno
Franzini,
Carlo
Guardiani
.633
40.3
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
Howard H. Chen, David D. Ling
.638
Session
41
Technology-Dependent Optimization for Performance and Power
Chair:
Gabriele
Saucier
Organizers: Jason Cong,
Gabriele
Saucier
41.1
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of
Sequential Circuits
Jason Cong, Chang Wu
.644
41.2
Technology-Dependent Transformations for Low-Power Synthesis
Rajendran Panda, FaridN. Najm
.650
41.3
Low Power FPGA Design
-
A Re-engineering Approach
Chau-Shen Chen, TingTing Hwang, C.L. Liu
.656
41.4
Post-Layout Logic Restructuring for Performance Optimization
Yt-Min Jiang, Angela
Krstić,
Kwang-Ting Cheng,
Małgorzata Marek-Sadowska
.662
41.5
Layout Driven Re-Synthesis for Low Power Consumption LSIs
Masako Murofushi, Takashi Ishioka,
Masami
Murakata,
Takashi Mitsuhashi
.666
xxvii
Session
42
CAD Issues for Micro-Electro-Mechanical Systems
Chair:
Randolph
E.
Han-
Organizers: Randolph
E.
Harr, Jacob
White
42.1
Embedded
Tutorial:
Overview of Microelectromechanical Systems and Design
Processes
William
С
Tang
.670
42.2
CAD and Foundries for Microsystems
J. M.
Кагат, В.
Courtois, H. Boutamine, P.
Drake,
A.
Poppe,
V.
Székely,
M. Rencz,
K.
Hofmann,
M. Glesner
.674
42.3
Structured
Design
of
Microelectromechanical Systems
Tamal
Mukherjee, Gary K. Fedder.
.680
42.4
Algorithms for Coupled
Domain MEMS Simulation
N.
Aluni, J.
White
.686
Session
43
Hardware/Software
Partitioning
Chair:
Rolf
Ernst
Organizers: Luciano
Lavagno,
Rajesh
К.
Gupta
43.1
A Hardware/Software Partitioner Using a Dynamically Determined Granularity
Jörg Henkel,
Rolf Ernst
.691
43.2
System-Level Synthesis of Low-Power Hard
Real-Time
Systems
Darko Kirovski, Miodrag Potkonjak
.697
43.3
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
.703
43.4
Data-Flow Assisted Behavioral Partitioning for Embedded Systems
Samir Agrawal, Rajesh K. Gupta
.709
43.5
Hardware/Software Partitioning and Pipelining
Smita
Bakshi, Daniel D. Gajski
.713
Session
44
44.1
Embedded Tutorial: Chip Parasitic Extraction and Signal Integrity Verification
Wayne W.-M. Dai
.717
Panel: Noise and Signal Integrity in Deep
Submicron
Design
Chair: William E. Guthrie
Organizer: Massoud Pedram
Panel Members: Rakesh Chadha, Jason Cong, Charlie Xiaoli Huang, Anirudh Devgan,
Tom Mozdzen, Andrew Yang
.720
Session
45
Designing High Performance and Low Power Microprocessors
Using Full Custom Techniques
Chair: Anantha
Chandrakasan
Organizer: Anantha
Chandrakasan
45.1
Designing High Performance CMOS Microprocessors Using Full Custom
Techniques
William J.
Grundmann,
Dan Dobberpuhl, Randy L.
Alimon,
Nicholas L. Rethman
.722
Session 46
Formal
Verification Techniques
Chair: Gary Hachte]
Organizers: Andreas Kuehlmann,
Fabio Somenzi
46.1
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for
Symbolic Traversal of Large Circuits
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno,
Stefano
Quer.728
46.2
An Efficient Assertion Checker for Combinational Properties
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
.734
46.3
Toward Formalizing a Validation Methodology Using Simulation Coverage
Aarti Gupta, Sharad Malik, Pranav Ashar
.740
Session
47
Placement Techniques
Chair:
Małgorzata Marek-Sadowska
Organizers: Patrick Groeneveld,
Antun
Domic
47.1
Algorithms for Large-Scale Flat Placement
Jens Vygen
.746
Xl.2
Quadratic Placement Revisited
C. J.
Alpert,
T.
Chan,
D.
J.-H. Huang, I. Markov, K. Yan
.752
47.3
Unification of Budgeting and Placement
Majid Sarrafzadeh, David
Knol,
Gustavo Tellez
.758
47.4
Cluster Refinement for Block Placement
Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
.762
Session
48
Panel: The EDA Startup Experience: Financing the Venture
Chair:
A. K. Kalekos
Organizer: Mike Murray
Panel Members: Marty Walker, Penny
Herscher, Lucio
Lanza, Peter
Odrina,
John Cooper, Gerrald Langeler
.766
Session
49
Heterogeneous System Analysis
Chairs: Randolph E.
Harr,
Richard Smith
Organizers: David Blaauw, Jan M. Rabaey
49.1
Computer-Aided Design of Free-Space Opto-Electronic Systems
S. P.
Levitán,
P. J.
Marchand, T.
P.
Kurzweg,
M. A. Rempel,
D. M.
Chiamili.
С.
Fan,
F.
В.
McCormick
.768
49.2
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach
Matthias Bauer, Wolfgang
Ecker.774
49.3
An Embedded System Case Study: The Firm Ware Development Environment for a
Multimedia Audio Processor
Clifford
Liem,
Marco
Cornem,
Miguel
Santana.
Pierre
Paulin,
Ahmed Jerraya,
Jean-Marc Gentit, Jean Lopez,
Xavier
Figari,
Laurent
Bergher.780 |
| any_adam_object | 1 |
| author_corporate | Design Automation Conference (Association for Computing Machinery) Anaheim, Calif |
| author_corporate_role | aut |
| author_facet | Design Automation Conference (Association for Computing Machinery) Anaheim, Calif |
| author_sort | Design Automation Conference (Association for Computing Machinery) Anaheim, Calif |
| building | Verbundindex |
| bvnumber | BV011570069 |
| classification_rvk | SS 1997 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)634507831 (DE-599)BVBBV011570069 |
| discipline | Informatik |
| format | Conference Proceeding Book |
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| genre_facet | Konferenzschrift 1997 Anaheim Calif. |
| id | DE-604.BV011570069 |
| illustrated | Illustrated |
| indexdate | 2025-01-20T15:01:32Z |
| institution | BVB |
| institution_GND | (DE-588)5251559-X |
| isbn | 0897919203 0780340930 0780340949 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007790076 |
| oclc_num | 634507831 |
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| owner_facet | DE-91G DE-BY-TUM DE-91 DE-BY-TUM DE-20 DE-739 DE-634 |
| physical | XXIX, 788 S. Ill., graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | IEEE |
| record_format | marc |
| spelling | Design Automation Conference (Association for Computing Machinery) 34 1997 Anaheim, Calif. Verfasser (DE-588)5251559-X aut Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 34th Design Automation Conference Piscataway, NY IEEE 1997 XXIX, 788 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1997 Anaheim Calif. gnd-content VLSI (DE-588)4117388-0 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007790076&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)1071861417 |
| title | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 |
| title_auth | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 |
| title_exact_search | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 |
| title_full | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 34th Design Automation Conference |
| title_fullStr | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 34th Design Automation Conference |
| title_full_unstemmed | Proceedings 1997 Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 34th Design Automation Conference |
| title_short | Proceedings 1997 |
| title_sort | proceedings 1997 anaheim convention center anaheim ca june 9 13 1997 |
| title_sub | Anaheim Convention Center, Anaheim, CA ; June 9 - 13, 1997 |
| topic | VLSI (DE-588)4117388-0 gnd |
| topic_facet | VLSI Konferenzschrift 1997 Anaheim Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007790076&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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